//Version: 1.0.0.1
DRV_DEF_M(FxPcs,8)
DRV_DEF_SDK_D(FxPcs,8,FxPcsCfg,0x0008,OP_DIRECT,TBL_SRAM,1,2,0x08030000,0x08030100,0x08030200,0x08030300,0x08030400,0x08030500,0x08030600,0x08030700)
DRV_DEF_SDK_F(FxPcs,8,FxPcsCfg,cfgFxLinkEnable,1,{0,0})
DRV_DEF_SDK_F(FxPcs,8,FxPcsCfg,cfgFxLinkStableTimer,8,{8,15})
DRV_DEF_SDK_F(FxPcs,8,FxPcsCfg,cfgFxRxBadTransThrd,8,{48,55})
DRV_DEF_SDK_F(FxPcs,8,FxPcsCfg,cfgFxRxEdgeDistVec,10,{32,41})
DRV_DEF_SDK_F(FxPcs,8,FxPcsCfg,cfgFxRxFaultEn,1,{1,1})
DRV_DEF_SDK_F(FxPcs,8,FxPcsCfg,cfgFxRxGlitchFilterEn,1,{63,63})
DRV_DEF_SDK_F(FxPcs,8,FxPcsCfg,cfgFxRxGoodTransThrd,8,{16,23})
DRV_DEF_SDK_F(FxPcs,8,FxPcsCfg,cfgFxRxNoTransThrd,8,{24,31})
DRV_DEF_SDK_F(FxPcs,8,FxPcsCfg,cfgFxTxFaultEn,1,{4,4})
DRV_DEF_SDK_F(FxPcs,8,FxPcsCfg,cfgFxTxForceLinkStatus,1,{5,5})

DRV_DEF_SDK_D(FxPcs,8,FxPcsRefPulseCfg,0x0008,OP_DIRECT,TBL_SRAM,1,2,0x08030030,0x08030130,0x08030230,0x08030330,0x08030430,0x08030530,0x08030630,0x08030730)
DRV_DEF_SDK_F(FxPcs,8,FxPcsRefPulseCfg,cfgRefDivLinkPulse,24,{0,23})
DRV_DEF_SDK_F(FxPcs,8,FxPcsRefPulseCfg,cfgResetDivLinkPulse,1,{24,24})
DRV_DEF_SDK_F(FxPcs,8,FxPcsRefPulseCfg,filterTimerCntCfg,8,{32,39})
DRV_DEF_SDK_F(FxPcs,8,FxPcsRefPulseCfg,linkFilterEn,1,{40,40})

DRV_DEF_D(FxPcs,8,FxPcsReserved,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x08030008,0x08030108,0x08030208,0x08030308,0x08030408,0x08030508,0x08030608,0x08030708)
DRV_DEF_F(FxPcs,8,FxPcsReserved,reserved,32,{0,31})

DRV_DEF_SDK_D(FxPcs,8,FxPcsSerdesCfg,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x0803000c,0x0803010c,0x0803020c,0x0803030c,0x0803040c,0x0803050c,0x0803060c,0x0803070c)
DRV_DEF_SDK_F(FxPcs,8,FxPcsSerdesCfg,forceRelock,1,{2,2})
DRV_DEF_SDK_F(FxPcs,8,FxPcsSerdesCfg,forceSignalDetect,1,{1,1})
DRV_DEF_SDK_F(FxPcs,8,FxPcsSerdesCfg,sigDetActiveValue,1,{0,0})

DRV_DEF_SDK_D(FxPcs,8,FxPcsSoftRst,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x08030020,0x08030120,0x08030220,0x08030320,0x08030420,0x08030520,0x08030620,0x08030720)
DRV_DEF_SDK_F(FxPcs,8,FxPcsSoftRst,fxPcsRxSoftRst,1,{0,0})
DRV_DEF_SDK_F(FxPcs,8,FxPcsSoftRst,fxPcsTxSoftRst,1,{1,1})

DRV_DEF_SDK_D(FxPcs,8,FxPcsStatus,0x000c,OP_DIRECT,TBL_SRAM,1,3,0x08030010,0x08030110,0x08030210,0x08030310,0x08030410,0x08030510,0x08030610,0x08030710)
DRV_DEF_SDK_F(FxPcs,8,FxPcsStatus,dbgFxLinkStatus,1,{0,0})
DRV_DEF_SDK_F(FxPcs,8,FxPcsStatus,dbgFxRxBadTransCnt,8,{72,79})
DRV_DEF_SDK_F(FxPcs,8,FxPcsStatus,dbgFxRxBitDropCnt,4,{88,91})
DRV_DEF_SDK_F(FxPcs,8,FxPcsStatus,dbgFxRxBitGlitchCnt,4,{44,47})
DRV_DEF_SDK_F(FxPcs,8,FxPcsStatus,dbgFxRxBitLock,1,{63,63})
DRV_DEF_SDK_F(FxPcs,8,FxPcsStatus,dbgFxRxBitsDepth,3,{92,94})
DRV_DEF_SDK_F(FxPcs,8,FxPcsStatus,dbgFxRxBitsFsm,3,{4,6})
DRV_DEF_SDK_F(FxPcs,8,FxPcsStatus,dbgFxRxDecodeFsm,4,{8,11})
DRV_DEF_SDK_F(FxPcs,8,FxPcsStatus,dbgFxRxErrorCnt,4,{40,43})
DRV_DEF_SDK_F(FxPcs,8,FxPcsStatus,dbgFxRxGoodTransCnt,8,{80,87})
DRV_DEF_SDK_F(FxPcs,8,FxPcsStatus,dbgFxRxNoTransCnt,8,{64,71})
DRV_DEF_SDK_F(FxPcs,8,FxPcsStatus,dbgFxRxSamp2BitsCnt,4,{32,35})
DRV_DEF_SDK_F(FxPcs,8,FxPcsStatus,dbgFxRxSkipBitCnt,4,{36,39})
DRV_DEF_SDK_F(FxPcs,8,FxPcsStatus,dbgFxTxEncodeFsm,4,{12,15})

//Version: 0.0.0.0
DRV_DEF_M(Gpio,1)
DRV_DEF_D(Gpio,1,GpioDebCnt,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x08011034)
DRV_DEF_F(Gpio,1,GpioDebCnt,cfgGpioDebCnt,4,{0,3})

DRV_DEF_D(Gpio,1,GpioDebCtl,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x08011030)
DRV_DEF_F(Gpio,1,GpioDebCtl,cfgDebEn,8,{0,7})

DRV_DEF_D(Gpio,1,GpioEoiCtl,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x08011028)
DRV_DEF_F(Gpio,1,GpioEoiCtl,cfgIntrClear,8,{0,7})

DRV_DEF_D(Gpio,1,GpioIntrEn,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x08011010)
DRV_DEF_F(Gpio,1,GpioIntrEn,cfgIntrEn,8,{0,7})

DRV_DEF_D(Gpio,1,GpioIntrLevel,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x08011018)
DRV_DEF_F(Gpio,1,GpioIntrLevel,cfgIntrLevel,8,{0,7})

DRV_DEF_D(Gpio,1,GpioIntrMask,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x08011014)
DRV_DEF_F(Gpio,1,GpioIntrMask,cfgIntrMask,8,{0,7})

DRV_DEF_D(Gpio,1,GpioIntrPolarity,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x0801101c)
DRV_DEF_F(Gpio,1,GpioIntrPolarity,cfgIntrPolarity,8,{0,7})

DRV_DEF_D(Gpio,1,GpioIntrRaw,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x08011024)
DRV_DEF_F(Gpio,1,GpioIntrRaw,gpioIntrRaw,8,{0,7})

DRV_DEF_D(Gpio,1,GpioIntrStatus,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x08011020)
DRV_DEF_F(Gpio,1,GpioIntrStatus,gpioIntrStatus,8,{0,7})

DRV_DEF_SDK_D(Gpio,1,GpioOutData,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x08011000)
DRV_DEF_SDK_F(Gpio,1,GpioOutData,cfgOutData,8,{0,7})

DRV_DEF_SDK_D(Gpio,1,GpioOutEn,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x08011004)
DRV_DEF_SDK_F(Gpio,1,GpioOutEn,cfgOutEn,8,{0,7})

DRV_DEF_SDK_D(Gpio,1,GpioReadData,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x08011008)
DRV_DEF_SDK_F(Gpio,1,GpioReadData,gpioReadData,8,{0,7})

DRV_DEF_SDK_D(Gpio,1,GpioVerId,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x08011080)
DRV_DEF_SDK_F(Gpio,1,GpioVerId,gpioVerId,4,{0,3})

//Version: 0.0.0.0
DRV_DEF_M(Led,1)
DRV_DEF_SDK_D(Led,1,LedBlinkCfg,0x0008,OP_DIRECT,TBL_SRAM,1,2,0x08010410)
DRV_DEF_SDK_F(Led,1,LedBlinkCfg,blinkOffInterval,32,{0,31})
DRV_DEF_SDK_F(Led,1,LedBlinkCfg,blinkOnInterval,32,{32,63})

DRV_DEF_D(Led,1,LedCfgAsyncFifoThrd,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x08010418)
DRV_DEF_F(Led,1,LedCfgAsyncFifoThrd,cfgAsyncFifoThrd,4,{0,3})

DRV_DEF_SDK_D(Led,1,LedCfgCalCtl,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x0801041c)
DRV_DEF_SDK_F(Led,1,LedCfgCalCtl,walkerStop,1,{0,0})

DRV_DEF_SDK_D(Led,1,LedInit,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x08010420)
DRV_DEF_SDK_F(Led,1,LedInit,init,1,{0,0})

DRV_DEF_SDK_D(Led,1,LedInitDone,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x08010424)
DRV_DEF_SDK_F(Led,1,LedInitDone,initDone,1,{0,0})

DRV_DEF_D(Led,1,LedLightMode,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x08010428)
DRV_DEF_F(Led,1,LedLightMode,cpuMode,1,{0,0})

DRV_DEF_SDK_D(Led,1,LedPolarityCfg,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x0801042c)
DRV_DEF_SDK_F(Led,1,LedPolarityCfg,polarityInv,1,{0,0})

DRV_DEF_SDK_D(Led,1,LedPortRange,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x08010440)
DRV_DEF_SDK_F(Led,1,LedPortRange,portEndIndex,5,{8,12})
DRV_DEF_SDK_F(Led,1,LedPortRange,portStartIndex,5,{0,4})

DRV_DEF_SDK_D(Led,1,LedRawStatusCfg,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x08010444)
DRV_DEF_SDK_F(Led,1,LedRawStatusCfg,rawStatusEn,1,{0,0})

DRV_DEF_SDK_D(Led,1,LedRefreshInterval,0x0008,OP_DIRECT,TBL_SRAM,1,2,0x08010448)
DRV_DEF_SDK_F(Led,1,LedRefreshInterval,refreshEn,1,{32,32})
DRV_DEF_SDK_F(Led,1,LedRefreshInterval,refreshInterval,32,{0,31})

DRV_DEF_D(Led,1,LedReserved,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x08010450)
DRV_DEF_F(Led,1,LedReserved,reserved,16,{0,15})

DRV_DEF_SDK_D(Led,1,LedSampleInterval,0x0008,OP_DIRECT,TBL_SRAM,1,2,0x08010458)
DRV_DEF_SDK_F(Led,1,LedSampleInterval,histogramEn,1,{36,36})
DRV_DEF_SDK_F(Led,1,LedSampleInterval,sampleEn,1,{32,32})
DRV_DEF_SDK_F(Led,1,LedSampleInterval,sampleInterval,32,{0,31})

DRV_DEF_SDK_D(Led,1,LedCfgPortMode,0x0004,OP_DIRECT,TBL_SRAM,32,1,0x08010500)
DRV_DEF_SDK_F(Led,1,LedCfgPortMode,primaryLedMode,4,{0,3})
DRV_DEF_SDK_F(Led,1,LedCfgPortMode,secondaryLedModeEn,1,{8,8})
DRV_DEF_SDK_F(Led,1,LedCfgPortMode,secondaryLedMode,4,{4,7})

DRV_DEF_SDK_D(Led,1,LedCfgPortSeqMap,0x0004,OP_DIRECT,TBL_SRAM,32,1,0x08010580)
DRV_DEF_SDK_F(Led,1,LedCfgPortSeqMap,macId,8,{0,7})

DRV_DEF_D(Led,1,LedInterruptNormal,0x0004,OP_DIRECT,TBL_SRAM,4,1,0x08010400)
DRV_DEF_F(Led,1,LedInterruptNormal,ledAsyncFifoOverrun,1,{0,0})

DRV_DEF_D(Led,1,LedMacStatusLock,0x0004,OP_DIRECT,TBL_SRAM,32,1,0x08010480)
DRV_DEF_F(Led,1,LedMacStatusLock,macActivStatus,2,{2,3})
DRV_DEF_F(Led,1,LedMacStatusLock,macLinkStatus,2,{0,1})

//Version: 0.0.0.0
DRV_DEF_M(Mdio,1)
DRV_DEF_SDK_D(Mdio,1,MdioCfg,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x0801000c)
DRV_DEF_SDK_F(Mdio,1,MdioCfg,mdioInDly,4,{8,11})
DRV_DEF_SDK_F(Mdio,1,MdioCfg,mdioMacPre,6,{0,5})
DRV_DEF_SDK_F(Mdio,1,MdioCfg,mdioNetSel,1,{12,12})

DRV_DEF_SDK_D(Mdio,1,MdioCmd,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x08010000)
DRV_DEF_SDK_F(Mdio,1,MdioCmd,dataCmd,16,{0,15})
DRV_DEF_SDK_F(Mdio,1,MdioCmd,opCodeCmd,2,{26,27})
DRV_DEF_SDK_F(Mdio,1,MdioCmd,phyAddCmd,5,{21,25})
DRV_DEF_SDK_F(Mdio,1,MdioCmd,regAddCmd,5,{16,20})

DRV_DEF_D(Mdio,1,MdioReserved,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x08010010)
DRV_DEF_F(Mdio,1,MdioReserved,reserved,16,{0,15})

DRV_DEF_SDK_D(Mdio,1,MdioStart,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x08010004)
DRV_DEF_SDK_F(Mdio,1,MdioStart,startCmd,2,{0,1})

DRV_DEF_SDK_D(Mdio,1,MdioStatus,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x08010008)
DRV_DEF_SDK_F(Mdio,1,MdioStatus,mdioCmdDone,1,{16,16})
DRV_DEF_SDK_F(Mdio,1,MdioStatus,mdioReadData,16,{0,15})

//Version: 1.0.0.1
DRV_DEF_M(QsgmiiPcs,4)
DRV_DEF_SDK_D(QsgmiiPcs,4,QsgmiiPcsAneg0Cfg,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x08032058,0x08032158,0x08032258,0x08032358)
DRV_DEF_SDK_F(QsgmiiPcs,4,QsgmiiPcsAneg0Cfg,anEnable0,1,{0,0})
DRV_DEF_SDK_F(QsgmiiPcs,4,QsgmiiPcsAneg0Cfg,anParallelDetectEn0,1,{20,20})
DRV_DEF_SDK_F(QsgmiiPcs,4,QsgmiiPcsAneg0Cfg,anRemoteLinkupEn0,1,{16,16})
DRV_DEF_SDK_F(QsgmiiPcs,4,QsgmiiPcsAneg0Cfg,anRestart0,1,{1,1})
DRV_DEF_SDK_F(QsgmiiPcs,4,QsgmiiPcsAneg0Cfg,anegMode0,2,{2,3})
DRV_DEF_SDK_F(QsgmiiPcs,4,QsgmiiPcsAneg0Cfg,ignoreAnegErr0,1,{5,5})
DRV_DEF_SDK_F(QsgmiiPcs,4,QsgmiiPcsAneg0Cfg,ignoreLinkFailure0,1,{4,4})
DRV_DEF_SDK_F(QsgmiiPcs,4,QsgmiiPcsAneg0Cfg,linkTimerCntCfg0,8,{24,31})
DRV_DEF_SDK_F(QsgmiiPcs,4,QsgmiiPcsAneg0Cfg,localEeeAbility0,1,{10,10})
DRV_DEF_SDK_F(QsgmiiPcs,4,QsgmiiPcsAneg0Cfg,localEeeClkStop0,1,{11,11})
DRV_DEF_SDK_F(QsgmiiPcs,4,QsgmiiPcsAneg0Cfg,localOffline0,1,{6,6})
DRV_DEF_SDK_F(QsgmiiPcs,4,QsgmiiPcsAneg0Cfg,localPauseAbility0,2,{12,13})
DRV_DEF_SDK_F(QsgmiiPcs,4,QsgmiiPcsAneg0Cfg,localSpeedMode0,2,{8,9})
DRV_DEF_SDK_F(QsgmiiPcs,4,QsgmiiPcsAneg0Cfg,txConfigReg14bitCfg0,1,{14,14})

DRV_DEF_SDK_D(QsgmiiPcs,4,QsgmiiPcsAneg1Cfg,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x0803204c,0x0803214c,0x0803224c,0x0803234c)
DRV_DEF_SDK_F(QsgmiiPcs,4,QsgmiiPcsAneg1Cfg,anEnable1,1,{0,0})
DRV_DEF_SDK_F(QsgmiiPcs,4,QsgmiiPcsAneg1Cfg,anParallelDetectEn1,1,{20,20})
DRV_DEF_SDK_F(QsgmiiPcs,4,QsgmiiPcsAneg1Cfg,anRemoteLinkupEn1,1,{16,16})
DRV_DEF_SDK_F(QsgmiiPcs,4,QsgmiiPcsAneg1Cfg,anRestart1,1,{1,1})
DRV_DEF_SDK_F(QsgmiiPcs,4,QsgmiiPcsAneg1Cfg,anegMode1,2,{2,3})
DRV_DEF_SDK_F(QsgmiiPcs,4,QsgmiiPcsAneg1Cfg,ignoreAnegErr1,1,{5,5})
DRV_DEF_SDK_F(QsgmiiPcs,4,QsgmiiPcsAneg1Cfg,ignoreLinkFailure1,1,{4,4})
DRV_DEF_SDK_F(QsgmiiPcs,4,QsgmiiPcsAneg1Cfg,linkTimerCntCfg1,8,{24,31})
DRV_DEF_SDK_F(QsgmiiPcs,4,QsgmiiPcsAneg1Cfg,localEeeAbility1,1,{10,10})
DRV_DEF_SDK_F(QsgmiiPcs,4,QsgmiiPcsAneg1Cfg,localEeeClkStop1,1,{11,11})
DRV_DEF_SDK_F(QsgmiiPcs,4,QsgmiiPcsAneg1Cfg,localOffline1,1,{6,6})
DRV_DEF_SDK_F(QsgmiiPcs,4,QsgmiiPcsAneg1Cfg,localPauseAbility1,2,{12,13})
DRV_DEF_SDK_F(QsgmiiPcs,4,QsgmiiPcsAneg1Cfg,localSpeedMode1,2,{8,9})
DRV_DEF_SDK_F(QsgmiiPcs,4,QsgmiiPcsAneg1Cfg,txConfigReg14bitCfg1,1,{14,14})

DRV_DEF_SDK_D(QsgmiiPcs,4,QsgmiiPcsAneg2Cfg,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x08032048,0x08032148,0x08032248,0x08032348)
DRV_DEF_SDK_F(QsgmiiPcs,4,QsgmiiPcsAneg2Cfg,anEnable2,1,{0,0})
DRV_DEF_SDK_F(QsgmiiPcs,4,QsgmiiPcsAneg2Cfg,anParallelDetectEn2,1,{20,20})
DRV_DEF_SDK_F(QsgmiiPcs,4,QsgmiiPcsAneg2Cfg,anRemoteLinkupEn2,1,{16,16})
DRV_DEF_SDK_F(QsgmiiPcs,4,QsgmiiPcsAneg2Cfg,anRestart2,1,{1,1})
DRV_DEF_SDK_F(QsgmiiPcs,4,QsgmiiPcsAneg2Cfg,anegMode2,2,{2,3})
DRV_DEF_SDK_F(QsgmiiPcs,4,QsgmiiPcsAneg2Cfg,ignoreAnegErr2,1,{5,5})
DRV_DEF_SDK_F(QsgmiiPcs,4,QsgmiiPcsAneg2Cfg,ignoreLinkFailure2,1,{4,4})
DRV_DEF_SDK_F(QsgmiiPcs,4,QsgmiiPcsAneg2Cfg,linkTimerCntCfg2,8,{24,31})
DRV_DEF_SDK_F(QsgmiiPcs,4,QsgmiiPcsAneg2Cfg,localEeeAbility2,1,{10,10})
DRV_DEF_SDK_F(QsgmiiPcs,4,QsgmiiPcsAneg2Cfg,localEeeClkStop2,1,{11,11})
DRV_DEF_SDK_F(QsgmiiPcs,4,QsgmiiPcsAneg2Cfg,localOffline2,1,{6,6})
DRV_DEF_SDK_F(QsgmiiPcs,4,QsgmiiPcsAneg2Cfg,localPauseAbility2,2,{12,13})
DRV_DEF_SDK_F(QsgmiiPcs,4,QsgmiiPcsAneg2Cfg,localSpeedMode2,2,{8,9})
DRV_DEF_SDK_F(QsgmiiPcs,4,QsgmiiPcsAneg2Cfg,txConfigReg14bitCfg2,1,{14,14})

DRV_DEF_SDK_D(QsgmiiPcs,4,QsgmiiPcsAneg3Cfg,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x08032050,0x08032150,0x08032250,0x08032350)
DRV_DEF_SDK_F(QsgmiiPcs,4,QsgmiiPcsAneg3Cfg,anEnable3,1,{0,0})
DRV_DEF_SDK_F(QsgmiiPcs,4,QsgmiiPcsAneg3Cfg,anParallelDetectEn3,1,{20,20})
DRV_DEF_SDK_F(QsgmiiPcs,4,QsgmiiPcsAneg3Cfg,anRemoteLinkupEn3,1,{16,16})
DRV_DEF_SDK_F(QsgmiiPcs,4,QsgmiiPcsAneg3Cfg,anRestart3,1,{1,1})
DRV_DEF_SDK_F(QsgmiiPcs,4,QsgmiiPcsAneg3Cfg,anegMode3,2,{2,3})
DRV_DEF_SDK_F(QsgmiiPcs,4,QsgmiiPcsAneg3Cfg,ignoreAnegErr3,1,{5,5})
DRV_DEF_SDK_F(QsgmiiPcs,4,QsgmiiPcsAneg3Cfg,ignoreLinkFailure3,1,{4,4})
DRV_DEF_SDK_F(QsgmiiPcs,4,QsgmiiPcsAneg3Cfg,linkTimerCntCfg3,8,{24,31})
DRV_DEF_SDK_F(QsgmiiPcs,4,QsgmiiPcsAneg3Cfg,localEeeAbility3,1,{10,10})
DRV_DEF_SDK_F(QsgmiiPcs,4,QsgmiiPcsAneg3Cfg,localEeeClkStop3,1,{11,11})
DRV_DEF_SDK_F(QsgmiiPcs,4,QsgmiiPcsAneg3Cfg,localOffline3,1,{6,6})
DRV_DEF_SDK_F(QsgmiiPcs,4,QsgmiiPcsAneg3Cfg,localPauseAbility3,2,{12,13})
DRV_DEF_SDK_F(QsgmiiPcs,4,QsgmiiPcsAneg3Cfg,localSpeedMode3,2,{8,9})
DRV_DEF_SDK_F(QsgmiiPcs,4,QsgmiiPcsAneg3Cfg,txConfigReg14bitCfg3,1,{14,14})

DRV_DEF_SDK_D(QsgmiiPcs,4,QsgmiiPcsCfg,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x08032054,0x08032154,0x08032254,0x08032354)
DRV_DEF_SDK_F(QsgmiiPcs,4,QsgmiiPcsCfg,disparityEn,1,{2,2})
DRV_DEF_SDK_F(QsgmiiPcs,4,QsgmiiPcsCfg,filterTimerCntCfg,8,{16,23})
DRV_DEF_SDK_F(QsgmiiPcs,4,QsgmiiPcsCfg,forceReLock,1,{4,4})
DRV_DEF_SDK_F(QsgmiiPcs,4,QsgmiiPcsCfg,forceSignalDetect,1,{1,1})
DRV_DEF_SDK_F(QsgmiiPcs,4,QsgmiiPcsCfg,linkFilterEn0,1,{24,24})
DRV_DEF_SDK_F(QsgmiiPcs,4,QsgmiiPcsCfg,linkFilterEn1,1,{25,25})
DRV_DEF_SDK_F(QsgmiiPcs,4,QsgmiiPcsCfg,linkFilterEn2,1,{26,26})
DRV_DEF_SDK_F(QsgmiiPcs,4,QsgmiiPcsCfg,linkFilterEn3,1,{27,27})
DRV_DEF_SDK_F(QsgmiiPcs,4,QsgmiiPcsCfg,reAlignEachEn,1,{3,3})
DRV_DEF_SDK_F(QsgmiiPcs,4,QsgmiiPcsCfg,sigDetActiveValue,1,{0,0})
DRV_DEF_SDK_F(QsgmiiPcs,4,QsgmiiPcsCfg,txXmitLoadUseAsyncFifo0,1,{9,9})
DRV_DEF_SDK_F(QsgmiiPcs,4,QsgmiiPcsCfg,txXmitLoadUseAsyncFifo1,1,{10,10})
DRV_DEF_SDK_F(QsgmiiPcs,4,QsgmiiPcsCfg,txXmitLoadUseAsyncFifo2,1,{11,11})
DRV_DEF_SDK_F(QsgmiiPcs,4,QsgmiiPcsCfg,txXmitLoadUseAsyncFifo3,1,{12,12})
DRV_DEF_SDK_F(QsgmiiPcs,4,QsgmiiPcsCfg,unidirectionEn0,1,{5,5})
DRV_DEF_SDK_F(QsgmiiPcs,4,QsgmiiPcsCfg,unidirectionEn1,1,{6,6})
DRV_DEF_SDK_F(QsgmiiPcs,4,QsgmiiPcsCfg,unidirectionEn2,1,{7,7})
DRV_DEF_SDK_F(QsgmiiPcs,4,QsgmiiPcsCfg,unidirectionEn3,1,{8,8})

DRV_DEF_D(QsgmiiPcs,4,QsgmiiPcsCodeErrCnt,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x0803205c,0x0803215c,0x0803225c,0x0803235c)
DRV_DEF_F(QsgmiiPcs,4,QsgmiiPcsCodeErrCnt,codeErrCnt0,8,{0,7})
DRV_DEF_F(QsgmiiPcs,4,QsgmiiPcsCodeErrCnt,codeErrCnt1,8,{8,15})
DRV_DEF_F(QsgmiiPcs,4,QsgmiiPcsCodeErrCnt,codeErrCnt2,8,{16,23})
DRV_DEF_F(QsgmiiPcs,4,QsgmiiPcsCodeErrCnt,codeErrCnt3,8,{24,31})

DRV_DEF_D(QsgmiiPcs,4,QsgmiiPcsK281PositionDbg,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x08032044,0x08032144,0x08032244,0x08032344)
DRV_DEF_F(QsgmiiPcs,4,QsgmiiPcsK281PositionDbg,k281PostionChgDbg,1,{0,0})
DRV_DEF_F(QsgmiiPcs,4,QsgmiiPcsK281PositionDbg,k281PostionLockDbg,4,{4,7})

DRV_DEF_SDK_D(QsgmiiPcs,4,QsgmiiPcsRefPulseCfg,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x08032060,0x08032160,0x08032260,0x08032360)
DRV_DEF_SDK_F(QsgmiiPcs,4,QsgmiiPcsRefPulseCfg,cfgRefDivLinkPulse,24,{0,23})
DRV_DEF_SDK_F(QsgmiiPcs,4,QsgmiiPcsRefPulseCfg,cfgResetDivLinkPulse,1,{24,24})

DRV_DEF_D(QsgmiiPcs,4,QsgmiiPcsReserved,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x08032040,0x08032140,0x08032240,0x08032340)
DRV_DEF_F(QsgmiiPcs,4,QsgmiiPcsReserved,reserved,32,{0,31})

DRV_DEF_SDK_D(QsgmiiPcs,4,QsgmiiPcsSoftRst,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x08032028,0x08032128,0x08032228,0x08032328)
DRV_DEF_SDK_F(QsgmiiPcs,4,QsgmiiPcsSoftRst,qsgmiiPcsRxSoftRst0,1,{0,0})
DRV_DEF_SDK_F(QsgmiiPcs,4,QsgmiiPcsSoftRst,qsgmiiPcsRxSoftRst1,1,{1,1})
DRV_DEF_SDK_F(QsgmiiPcs,4,QsgmiiPcsSoftRst,qsgmiiPcsRxSoftRst2,1,{2,2})
DRV_DEF_SDK_F(QsgmiiPcs,4,QsgmiiPcsSoftRst,qsgmiiPcsRxSoftRst3,1,{3,3})
DRV_DEF_SDK_F(QsgmiiPcs,4,QsgmiiPcsSoftRst,qsgmiiPcsTxSoftRst0,1,{4,4})
DRV_DEF_SDK_F(QsgmiiPcs,4,QsgmiiPcsSoftRst,qsgmiiPcsTxSoftRst1,1,{5,5})
DRV_DEF_SDK_F(QsgmiiPcs,4,QsgmiiPcsSoftRst,qsgmiiPcsTxSoftRst2,1,{6,6})
DRV_DEF_SDK_F(QsgmiiPcs,4,QsgmiiPcsSoftRst,qsgmiiPcsTxSoftRst3,1,{7,7})
DRV_DEF_SDK_F(QsgmiiPcs,4,QsgmiiPcsSoftRst,qsgmiiPcsTxSoftRst,1,{9,9})
DRV_DEF_SDK_F(QsgmiiPcs,4,QsgmiiPcsSoftRst,qsgmiiPmaRxSoftRst,1,{8,8})

DRV_DEF_SDK_D(QsgmiiPcs,4,QsgmiiPcsStatus0,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x08032030,0x08032130,0x08032230,0x08032330)
DRV_DEF_SDK_F(QsgmiiPcs,4,QsgmiiPcsStatus0,anComplete0,1,{1,1})
DRV_DEF_SDK_F(QsgmiiPcs,4,QsgmiiPcsStatus0,anLinkFailure0,1,{2,2})
DRV_DEF_SDK_F(QsgmiiPcs,4,QsgmiiPcsStatus0,anLinkStatus0,1,{0,0})
DRV_DEF_SDK_F(QsgmiiPcs,4,QsgmiiPcsStatus0,anRxRemoteCfg0,16,{16,31})
DRV_DEF_SDK_F(QsgmiiPcs,4,QsgmiiPcsStatus0,anegState0,3,{4,6})
DRV_DEF_SDK_F(QsgmiiPcs,4,QsgmiiPcsStatus0,rxLpiState0,1,{7,7})
DRV_DEF_SDK_F(QsgmiiPcs,4,QsgmiiPcsStatus0,syncStatus0,1,{3,3})

DRV_DEF_SDK_D(QsgmiiPcs,4,QsgmiiPcsStatus1,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x0803203c,0x0803213c,0x0803223c,0x0803233c)
DRV_DEF_SDK_F(QsgmiiPcs,4,QsgmiiPcsStatus1,anComplete1,1,{1,1})
DRV_DEF_SDK_F(QsgmiiPcs,4,QsgmiiPcsStatus1,anLinkFailure1,1,{2,2})
DRV_DEF_SDK_F(QsgmiiPcs,4,QsgmiiPcsStatus1,anLinkStatus1,1,{0,0})
DRV_DEF_SDK_F(QsgmiiPcs,4,QsgmiiPcsStatus1,anRxRemoteCfg1,16,{16,31})
DRV_DEF_SDK_F(QsgmiiPcs,4,QsgmiiPcsStatus1,anegState1,3,{4,6})
DRV_DEF_SDK_F(QsgmiiPcs,4,QsgmiiPcsStatus1,rxLpiState1,1,{7,7})
DRV_DEF_SDK_F(QsgmiiPcs,4,QsgmiiPcsStatus1,syncStatus1,1,{3,3})

DRV_DEF_SDK_D(QsgmiiPcs,4,QsgmiiPcsStatus2,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x08032038,0x08032138,0x08032238,0x08032338)
DRV_DEF_SDK_F(QsgmiiPcs,4,QsgmiiPcsStatus2,anComplete2,1,{1,1})
DRV_DEF_SDK_F(QsgmiiPcs,4,QsgmiiPcsStatus2,anLinkFailure2,1,{2,2})
DRV_DEF_SDK_F(QsgmiiPcs,4,QsgmiiPcsStatus2,anLinkStatus2,1,{0,0})
DRV_DEF_SDK_F(QsgmiiPcs,4,QsgmiiPcsStatus2,anRxRemoteCfg2,16,{16,31})
DRV_DEF_SDK_F(QsgmiiPcs,4,QsgmiiPcsStatus2,anegState2,3,{4,6})
DRV_DEF_SDK_F(QsgmiiPcs,4,QsgmiiPcsStatus2,rxLpiState2,1,{7,7})
DRV_DEF_SDK_F(QsgmiiPcs,4,QsgmiiPcsStatus2,syncStatus2,1,{3,3})

DRV_DEF_SDK_D(QsgmiiPcs,4,QsgmiiPcsStatus3,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x08032034,0x08032134,0x08032234,0x08032334)
DRV_DEF_SDK_F(QsgmiiPcs,4,QsgmiiPcsStatus3,anComplete3,1,{1,1})
DRV_DEF_SDK_F(QsgmiiPcs,4,QsgmiiPcsStatus3,anLinkFailure3,1,{2,2})
DRV_DEF_SDK_F(QsgmiiPcs,4,QsgmiiPcsStatus3,anLinkStatus3,1,{0,0})
DRV_DEF_SDK_F(QsgmiiPcs,4,QsgmiiPcsStatus3,anRxRemoteCfg3,16,{16,31})
DRV_DEF_SDK_F(QsgmiiPcs,4,QsgmiiPcsStatus3,anegState3,3,{4,6})
DRV_DEF_SDK_F(QsgmiiPcs,4,QsgmiiPcsStatus3,rxLpiState3,1,{7,7})
DRV_DEF_SDK_F(QsgmiiPcs,4,QsgmiiPcsStatus3,syncStatus3,1,{3,3})

DRV_DEF_D(QsgmiiPcs,4,QsgmiiPcsInterruptNormal,0x0004,OP_DIRECT,TBL_SRAM,4,1,0x08032000,0x08032100,0x08032200,0x08032300)
DRV_DEF_F(QsgmiiPcs,4,QsgmiiPcsInterruptNormal,anComplete0,1,{0,0})
DRV_DEF_F(QsgmiiPcs,4,QsgmiiPcsInterruptNormal,anComplete1,1,{1,1})
DRV_DEF_F(QsgmiiPcs,4,QsgmiiPcsInterruptNormal,anComplete2,1,{2,2})
DRV_DEF_F(QsgmiiPcs,4,QsgmiiPcsInterruptNormal,anComplete3,1,{3,3})
DRV_DEF_F(QsgmiiPcs,4,QsgmiiPcsInterruptNormal,anRemoteAnegErr0,1,{12,12})
DRV_DEF_F(QsgmiiPcs,4,QsgmiiPcsInterruptNormal,anRemoteAnegErr1,1,{13,13})
DRV_DEF_F(QsgmiiPcs,4,QsgmiiPcsInterruptNormal,anRemoteAnegErr2,1,{14,14})
DRV_DEF_F(QsgmiiPcs,4,QsgmiiPcsInterruptNormal,anRemoteAnegErr3,1,{15,15})
DRV_DEF_F(QsgmiiPcs,4,QsgmiiPcsInterruptNormal,anRemoteLinkFailure0,1,{8,8})
DRV_DEF_F(QsgmiiPcs,4,QsgmiiPcsInterruptNormal,anRemoteLinkFailure1,1,{9,9})
DRV_DEF_F(QsgmiiPcs,4,QsgmiiPcsInterruptNormal,anRemoteLinkFailure2,1,{10,10})
DRV_DEF_F(QsgmiiPcs,4,QsgmiiPcsInterruptNormal,anRemoteLinkFailure3,1,{11,11})
DRV_DEF_F(QsgmiiPcs,4,QsgmiiPcsInterruptNormal,anRemoteOffline0,1,{4,4})
DRV_DEF_F(QsgmiiPcs,4,QsgmiiPcsInterruptNormal,anRemoteOffline1,1,{5,5})
DRV_DEF_F(QsgmiiPcs,4,QsgmiiPcsInterruptNormal,anRemoteOffline2,1,{6,6})
DRV_DEF_F(QsgmiiPcs,4,QsgmiiPcsInterruptNormal,anRemoteOffline3,1,{7,7})
DRV_DEF_F(QsgmiiPcs,4,QsgmiiPcsInterruptNormal,signalDetectLos,1,{16,16})
DRV_DEF_F(QsgmiiPcs,4,QsgmiiPcsInterruptNormal,txXmitLoadAsyncFifoOverrun0,1,{17,17})
DRV_DEF_F(QsgmiiPcs,4,QsgmiiPcsInterruptNormal,txXmitLoadAsyncFifoOverrun1,1,{18,18})
DRV_DEF_F(QsgmiiPcs,4,QsgmiiPcsInterruptNormal,txXmitLoadAsyncFifoOverrun2,1,{19,19})
DRV_DEF_F(QsgmiiPcs,4,QsgmiiPcsInterruptNormal,txXmitLoadAsyncFifoOverrun3,1,{20,20})

//Version: 0.0.0.0
DRV_DEF_M(Qspi,1)
DRV_DEF_D(Qspi,1,QspiAxiCtl,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x10000090)
DRV_DEF_F(Qspi,1,QspiAxiCtl,cfgProcTimer,16,{0,15})

DRV_DEF_D(Qspi,1,QspiAxiDebugStats,0x0008,OP_DIRECT,TBL_SRAM,1,2,0x100000c0)
DRV_DEF_F(Qspi,1,QspiAxiDebugStats,frMasterRdReqCnt,4,{12,15})
DRV_DEF_F(Qspi,1,QspiAxiDebugStats,frMasterWrDataCnt,4,{4,7})
DRV_DEF_F(Qspi,1,QspiAxiDebugStats,frMasterWrReqCnt,4,{0,3})
DRV_DEF_F(Qspi,1,QspiAxiDebugStats,regAckDataCnt,4,{20,23})
DRV_DEF_F(Qspi,1,QspiAxiDebugStats,regAckErrorCnt,4,{24,27})
DRV_DEF_F(Qspi,1,QspiAxiDebugStats,regAckTimeoutCnt,4,{28,31})
DRV_DEF_F(Qspi,1,QspiAxiDebugStats,regProcState,3,{32,34})
DRV_DEF_F(Qspi,1,QspiAxiDebugStats,toMasterRdDataCnt,4,{16,19})
DRV_DEF_F(Qspi,1,QspiAxiDebugStats,toMasterWrAckCnt,4,{8,11})

DRV_DEF_D(Qspi,1,QspiBaudRateCtl,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x10000050)
DRV_DEF_F(Qspi,1,QspiBaudRateCtl,divisor,10,{0,9})

DRV_DEF_D(Qspi,1,QspiClkCtl,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x10000054)
DRV_DEF_F(Qspi,1,QspiClkCtl,cPha,1,{4,4})
DRV_DEF_F(Qspi,1,QspiClkCtl,cPol,1,{0,0})

DRV_DEF_D(Qspi,1,QspiDebugStats,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x100000d8)
DRV_DEF_F(Qspi,1,QspiDebugStats,fsmStateDbg,12,{0,11})

DRV_DEF_D(Qspi,1,QspiEventStatus,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x100000dc)
DRV_DEF_F(Qspi,1,QspiEventStatus,qspiRxFifoAFull,1,{0,0})
DRV_DEF_F(Qspi,1,QspiEventStatus,qspiRxFifoNEmpty,1,{1,1})
DRV_DEF_F(Qspi,1,QspiEventStatus,qspiTxFifoAEmpty,1,{2,2})
DRV_DEF_F(Qspi,1,QspiEventStatus,qspiTxFifoNFull,1,{3,3})
DRV_DEF_F(Qspi,1,QspiEventStatus,spiProcDone,1,{4,4})

DRV_DEF_D(Qspi,1,QspiFifoCtl,0x0008,OP_DIRECT,TBL_SRAM,1,2,0x10000080)
DRV_DEF_F(Qspi,1,QspiFifoCtl,qspiRxFifoAFullThrd,7,{32,38})
DRV_DEF_F(Qspi,1,QspiFifoCtl,qspiTxFifoAEmptyThrd,7,{16,22})
DRV_DEF_F(Qspi,1,QspiFifoCtl,qspiTxFifoAFullThrd,7,{0,6})

DRV_DEF_D(Qspi,1,QspiFifoDepth,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x100000f4)
DRV_DEF_F(Qspi,1,QspiFifoDepth,qspiRxFifoFifoDepth,7,{0,6})
DRV_DEF_F(Qspi,1,QspiFifoDepth,qspiTxFifoFifoDepth,7,{7,13})

DRV_DEF_D(Qspi,1,QspiGapCtl,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x10000040)
DRV_DEF_F(Qspi,1,QspiGapCtl,ssAft,4,{8,11})
DRV_DEF_F(Qspi,1,QspiGapCtl,ssBef,4,{0,3})
DRV_DEF_F(Qspi,1,QspiGapCtl,ssGap,4,{16,19})

DRV_DEF_D(Qspi,1,QspiIoModeCtl,0x0010,OP_DIRECT,TBL_SRAM,1,4,0x10000060)
DRV_DEF_F(Qspi,1,QspiIoModeCtl,ioStep0CycleCfg,12,{0,11})
DRV_DEF_F(Qspi,1,QspiIoModeCtl,ioStep0LaneCfg,3,{20,22})
DRV_DEF_F(Qspi,1,QspiIoModeCtl,ioStep0OutEnCfg,4,{16,19})
DRV_DEF_F(Qspi,1,QspiIoModeCtl,ioStep1CycleCfg,12,{32,43})
DRV_DEF_F(Qspi,1,QspiIoModeCtl,ioStep1LaneCfg,3,{52,54})
DRV_DEF_F(Qspi,1,QspiIoModeCtl,ioStep1OutEnCfg,4,{48,51})
DRV_DEF_F(Qspi,1,QspiIoModeCtl,ioStep2CycleCfg,12,{64,75})
DRV_DEF_F(Qspi,1,QspiIoModeCtl,ioStep2LaneCfg,3,{84,86})
DRV_DEF_F(Qspi,1,QspiIoModeCtl,ioStep2OutEnCfg,4,{80,83})
DRV_DEF_F(Qspi,1,QspiIoModeCtl,ioStep3CycleCfg,12,{96,107})
DRV_DEF_F(Qspi,1,QspiIoModeCtl,ioStep3LaneCfg,3,{116,118})
DRV_DEF_F(Qspi,1,QspiIoModeCtl,ioStep3OutEnCfg,4,{112,115})

DRV_DEF_D(Qspi,1,QspiMiscCtl,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x1000005c)
DRV_DEF_F(Qspi,1,QspiMiscCtl,sout1Cfg,1,{2,2})
DRV_DEF_F(Qspi,1,QspiMiscCtl,sout2Cfg,1,{1,1})
DRV_DEF_F(Qspi,1,QspiMiscCtl,sout3Cfg,1,{0,0})
DRV_DEF_F(Qspi,1,QspiMiscCtl,spiXipMultEn,1,{31,31})

DRV_DEF_D(Qspi,1,QspiModeCtl,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x10000044)
DRV_DEF_F(Qspi,1,QspiModeCtl,ioModeEn,1,{0,0})
DRV_DEF_F(Qspi,1,QspiModeCtl,ppModeEn,1,{8,8})

DRV_DEF_D(Qspi,1,QspiPPCtl,0x0018,OP_DIRECT,TBL_SRAM,1,6,0x10000020)
DRV_DEF_F(Qspi,1,QspiPPCtl,ppAddrCode,32,{32,63})
DRV_DEF_F(Qspi,1,QspiPPCtl,ppAddrCycleCfg,12,{64,75})
DRV_DEF_F(Qspi,1,QspiPPCtl,ppAddrLaneCfg,3,{80,82})
DRV_DEF_F(Qspi,1,QspiPPCtl,ppCmdCode,8,{0,7})
DRV_DEF_F(Qspi,1,QspiPPCtl,ppCmdCycleCfg,12,{16,27})
DRV_DEF_F(Qspi,1,QspiPPCtl,ppCmdLaneCfg,3,{8,10})
DRV_DEF_F(Qspi,1,QspiPPCtl,ppDataCycleCfg,12,{160,171})
DRV_DEF_F(Qspi,1,QspiPPCtl,ppDataLaneCfg,3,{176,178})
DRV_DEF_F(Qspi,1,QspiPPCtl,ppDummyCode,32,{96,127})
DRV_DEF_F(Qspi,1,QspiPPCtl,ppDummyCycleCfg,12,{128,139})
DRV_DEF_F(Qspi,1,QspiPPCtl,ppDummyLaneCfg,3,{144,146})

DRV_DEF_D(Qspi,1,QspiProcCtl,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x10000048)
DRV_DEF_F(Qspi,1,QspiProcCtl,spiInProc,1,{0,0})

DRV_DEF_D(Qspi,1,QspiRxDataCtl,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x10000010)
DRV_DEF_F(Qspi,1,QspiRxDataCtl,rxData,32,{0,31})

DRV_DEF_D(Qspi,1,QspiSelectCtl,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x1000004c)
DRV_DEF_F(Qspi,1,QspiSelectCtl,chipSelOutEn,1,{8,8})
DRV_DEF_F(Qspi,1,QspiSelectCtl,chipSel,2,{0,1})

DRV_DEF_D(Qspi,1,QspiSystemCtl,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x10000058)
DRV_DEF_F(Qspi,1,QspiSystemCtl,masterEn,1,{0,0})

DRV_DEF_D(Qspi,1,QspiTxAddrCtl,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x10000004)
DRV_DEF_F(Qspi,1,QspiTxAddrCtl,txAddr,32,{0,31})

DRV_DEF_D(Qspi,1,QspiTxCmdCtl,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x10000000)
DRV_DEF_F(Qspi,1,QspiTxCmdCtl,txCmd,8,{0,7})

DRV_DEF_D(Qspi,1,QspiTxDataCtl,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x10000008)
DRV_DEF_F(Qspi,1,QspiTxDataCtl,txData,32,{0,31})

DRV_DEF_D(Qspi,1,QspiTxDummyCtl,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x1000000c)
DRV_DEF_F(Qspi,1,QspiTxDummyCtl,txDummy,32,{0,31})

DRV_DEF_D(Qspi,1,QspiXipCtl,0x0010,OP_DIRECT,TBL_SRAM,1,4,0x10000070)
DRV_DEF_F(Qspi,1,QspiXipCtl,xipAddrCycleCfg,12,{32,43})
DRV_DEF_F(Qspi,1,QspiXipCtl,xipAddrLaneCfg,3,{48,50})
DRV_DEF_F(Qspi,1,QspiXipCtl,xipCmdCode,8,{0,7})
DRV_DEF_F(Qspi,1,QspiXipCtl,xipCmdCycleCfg,12,{16,27})
DRV_DEF_F(Qspi,1,QspiXipCtl,xipCmdLaneCfg,3,{8,10})
DRV_DEF_F(Qspi,1,QspiXipCtl,xipDataLaneCfg,3,{116,118})
DRV_DEF_F(Qspi,1,QspiXipCtl,xipDummyCode,32,{64,95})
DRV_DEF_F(Qspi,1,QspiXipCtl,xipDummyCycleCfg,12,{96,107})
DRV_DEF_F(Qspi,1,QspiXipCtl,xipDummyLaneCfg,3,{112,114})

DRV_DEF_D(Qspi,1,QspiFuncInterrupt,0x0004,OP_DIRECT,TBL_SRAM,4,1,0x100000a0)
DRV_DEF_F(Qspi,1,QspiFuncInterrupt,qspiRxFifoAFull,1,{0,0})
DRV_DEF_F(Qspi,1,QspiFuncInterrupt,qspiRxFifoNEmpty,1,{1,1})
DRV_DEF_F(Qspi,1,QspiFuncInterrupt,qspiTxFifoAEmpty,1,{2,2})
DRV_DEF_F(Qspi,1,QspiFuncInterrupt,qspiTxFifoEmpty,1,{3,3})

DRV_DEF_D(Qspi,1,QspiInterruptFatal,0x0004,OP_DIRECT,TBL_SRAM,4,1,0x100000b0)
DRV_DEF_F(Qspi,1,QspiInterruptFatal,axiWrIdMismatchIntr,1,{5,5})
DRV_DEF_F(Qspi,1,QspiInterruptFatal,axiWrLenMismatchIntr,1,{4,4})
DRV_DEF_F(Qspi,1,QspiInterruptFatal,qspiRxFifoOverrun,1,{3,3})
DRV_DEF_F(Qspi,1,QspiInterruptFatal,qspiRxFifoUnderrun,1,{2,2})
DRV_DEF_F(Qspi,1,QspiInterruptFatal,qspiTxFifoOverrun,1,{1,1})
DRV_DEF_F(Qspi,1,QspiInterruptFatal,qspiTxFifoUnderrun,1,{0,0})

DRV_DEF_D(Qspi,1,QspiRxFifo,0x0004,OP_DIRECT,TBL_SRAM,64,1,0x10000200)
DRV_DEF_F(Qspi,1,QspiRxFifo,data,32,{0,31})

DRV_DEF_D(Qspi,1,QspiTxFifo,0x0004,OP_DIRECT,TBL_SRAM,64,1,0x10000100)
DRV_DEF_F(Qspi,1,QspiTxFifo,data,32,{0,31})

//Version: 1.0.0.1
DRV_DEF_M(SgmiiPcs,8)
DRV_DEF_SDK_D(SgmiiPcs,8,SgmiiPcsCfg,0x0008,OP_DIRECT,TBL_SRAM,1,2,0x08031030,0x08031130,0x08031230,0x08031330,0x08031430,0x08031530,0x08031630,0x08031730)
DRV_DEF_SDK_F(SgmiiPcs,8,SgmiiPcsCfg,anEnable,1,{0,0})
DRV_DEF_SDK_F(SgmiiPcs,8,SgmiiPcsCfg,anParallelDetectEn,1,{16,16})
DRV_DEF_SDK_F(SgmiiPcs,8,SgmiiPcsCfg,anRemoteLinkupEn,1,{17,17})
DRV_DEF_SDK_F(SgmiiPcs,8,SgmiiPcsCfg,anRestart,1,{1,1})
DRV_DEF_SDK_F(SgmiiPcs,8,SgmiiPcsCfg,anegMode,2,{2,3})
DRV_DEF_SDK_F(SgmiiPcs,8,SgmiiPcsCfg,filterTimerCntCfg,8,{32,39})
DRV_DEF_SDK_F(SgmiiPcs,8,SgmiiPcsCfg,ignoreAnegErr,1,{5,5})
DRV_DEF_SDK_F(SgmiiPcs,8,SgmiiPcsCfg,ignoreLinkFailure,1,{4,4})
DRV_DEF_SDK_F(SgmiiPcs,8,SgmiiPcsCfg,linkFilterEn,1,{40,40})
DRV_DEF_SDK_F(SgmiiPcs,8,SgmiiPcsCfg,linkTimerCntCfg,8,{24,31})
DRV_DEF_SDK_F(SgmiiPcs,8,SgmiiPcsCfg,localEeeAbility,1,{10,10})
DRV_DEF_SDK_F(SgmiiPcs,8,SgmiiPcsCfg,localEeeClkStop,1,{11,11})
DRV_DEF_SDK_F(SgmiiPcs,8,SgmiiPcsCfg,localOffline,1,{6,6})
DRV_DEF_SDK_F(SgmiiPcs,8,SgmiiPcsCfg,localPauseAbility,2,{12,13})
DRV_DEF_SDK_F(SgmiiPcs,8,SgmiiPcsCfg,localSpeedMode,3,{7,9})
DRV_DEF_SDK_F(SgmiiPcs,8,SgmiiPcsCfg,txConfigReg14bitCfg,1,{14,14})
DRV_DEF_SDK_F(SgmiiPcs,8,SgmiiPcsCfg,txXmitLoadUseAsyncFifo,1,{15,15})
DRV_DEF_SDK_F(SgmiiPcs,8,SgmiiPcsCfg,unidirectionEn,1,{18,18})

DRV_DEF_SDK_D(SgmiiPcs,8,SgmiiPcsRefPulseCfg,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x08031024,0x08031124,0x08031224,0x08031324,0x08031424,0x08031524,0x08031624,0x08031724)
DRV_DEF_SDK_F(SgmiiPcs,8,SgmiiPcsRefPulseCfg,cfgRefDivLinkPulse,24,{0,23})
DRV_DEF_SDK_F(SgmiiPcs,8,SgmiiPcsRefPulseCfg,cfgResetDivLinkPulse,1,{24,24})

DRV_DEF_D(SgmiiPcs,8,SgmiiPcsReserved,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x08031028,0x08031128,0x08031228,0x08031328,0x08031428,0x08031528,0x08031628,0x08031728)
DRV_DEF_F(SgmiiPcs,8,SgmiiPcsReserved,reserved,32,{0,31})

DRV_DEF_D(SgmiiPcs,8,SgmiiPcsSerdesCfg,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x0803101c,0x0803111c,0x0803121c,0x0803131c,0x0803141c,0x0803151c,0x0803161c,0x0803171c)
DRV_DEF_F(SgmiiPcs,8,SgmiiPcsSerdesCfg,forceRelock,1,{2,2})
DRV_DEF_F(SgmiiPcs,8,SgmiiPcsSerdesCfg,forceSignalDetect,1,{1,1})
DRV_DEF_F(SgmiiPcs,8,SgmiiPcsSerdesCfg,sigDetActiveValue,1,{0,0})

DRV_DEF_SDK_D(SgmiiPcs,8,SgmiiPcsSgmiiStatus,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x08031010,0x08031110,0x08031210,0x08031310,0x08031410,0x08031510,0x08031610,0x08031710)
DRV_DEF_SDK_F(SgmiiPcs,8,SgmiiPcsSgmiiStatus,anComplete,1,{1,1})
DRV_DEF_SDK_F(SgmiiPcs,8,SgmiiPcsSgmiiStatus,anLinkFailure,1,{6,6})
DRV_DEF_SDK_F(SgmiiPcs,8,SgmiiPcsSgmiiStatus,anLinkStatus,1,{0,0})
DRV_DEF_SDK_F(SgmiiPcs,8,SgmiiPcsSgmiiStatus,anRxRemoteCfg,16,{12,27})
DRV_DEF_SDK_F(SgmiiPcs,8,SgmiiPcsSgmiiStatus,anegState,3,{2,4})
DRV_DEF_SDK_F(SgmiiPcs,8,SgmiiPcsSgmiiStatus,codeErrCnt,4,{8,11})
DRV_DEF_SDK_F(SgmiiPcs,8,SgmiiPcsSgmiiStatus,sgmiiSyncStatus,1,{5,5})

DRV_DEF_SDK_D(SgmiiPcs,8,SgmiiPcsSoftRst,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x08031014,0x08031114,0x08031214,0x08031314,0x08031414,0x08031514,0x08031614,0x08031714)
DRV_DEF_SDK_F(SgmiiPcs,8,SgmiiPcsSoftRst,sgmiiPcsRxSoftRst,1,{0,0})
DRV_DEF_SDK_F(SgmiiPcs,8,SgmiiPcsSoftRst,sgmiiPcsTxSoftRst,1,{1,1})

DRV_DEF_D(SgmiiPcs,8,SgmiiPcsInterruptNormal,0x0004,OP_DIRECT,TBL_SRAM,4,1,0x08031000,0x08031100,0x08031200,0x08031300,0x08031400,0x08031500,0x08031600,0x08031700)
DRV_DEF_F(SgmiiPcs,8,SgmiiPcsInterruptNormal,anComplete,1,{0,0})
DRV_DEF_F(SgmiiPcs,8,SgmiiPcsInterruptNormal,anRemoteAnegErr,1,{3,3})
DRV_DEF_F(SgmiiPcs,8,SgmiiPcsInterruptNormal,anRemoteLinkFailure,1,{2,2})
DRV_DEF_F(SgmiiPcs,8,SgmiiPcsInterruptNormal,anRemoteOffline,1,{1,1})
DRV_DEF_F(SgmiiPcs,8,SgmiiPcsInterruptNormal,txXmitLoadAsyncFifoOverrun,1,{4,4})

//Version: 1.0.0.1
DRV_DEF_M(SupEfuse,1)
DRV_DEF_D(SupEfuse,1,EFuseCtl,0x0008,OP_DIRECT,TBL_SRAM,1,2,0x08011408)
DRV_DEF_F(SupEfuse,1,EFuseCtl,efuseDataReady,1,{4,4})
DRV_DEF_F(SupEfuse,1,EFuseCtl,efuseKey,32,{32,63})
DRV_DEF_F(SupEfuse,1,EFuseCtl,efuseProgBusy,1,{5,5})
DRV_DEF_F(SupEfuse,1,EFuseCtl,efuseWrComplete,1,{0,0})
DRV_DEF_F(SupEfuse,1,EFuseCtl,efuseWrEn,1,{1,1})

DRV_DEF_D(SupEfuse,1,EfuseCfg,0x0010,OP_DIRECT,TBL_SRAM,1,4,0x08011410)
DRV_DEF_F(SupEfuse,1,EfuseCfg,cfgEfusePsForceHigh,1,{28,28})
DRV_DEF_F(SupEfuse,1,EfuseCfg,cfgEfusePsForceLow,1,{29,29})
DRV_DEF_F(SupEfuse,1,EfuseCfg,cfgEfuseWrReserveAddr,8,{56,63})
DRV_DEF_F(SupEfuse,1,EfuseCfg,cfgThdPsCsWr,24,{96,119})
DRV_DEF_F(SupEfuse,1,EfuseCfg,cfgTpgm,12,{32,43})
DRV_DEF_F(SupEfuse,1,EfuseCfg,cfgTrd,8,{8,15})
DRV_DEF_F(SupEfuse,1,EfuseCfg,cfgTsq,8,{0,7})
DRV_DEF_F(SupEfuse,1,EfuseCfg,cfgTsuCsRd,8,{16,23})
DRV_DEF_F(SupEfuse,1,EfuseCfg,cfgTsuCsWr,8,{44,51})
DRV_DEF_F(SupEfuse,1,EfuseCfg,cfgTsuPsCsRd,4,{24,27})
DRV_DEF_F(SupEfuse,1,EfuseCfg,cfgTsuPsCsWr,24,{64,87})

DRV_DEF_D(SupEfuse,1,EFuseMem,0x0004,OP_DIRECT,TBL_SRAM,32,1,0x08011480)
DRV_DEF_F(SupEfuse,1,EFuseMem,data,8,{0,7})

//Version: 1.0.0.1
DRV_DEF_M(Sup,1)
DRV_DEF_D(Sup,1,ApbProcTimer,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x0800004c)
DRV_DEF_F(Sup,1,ApbProcTimer,cfgProcTimer,12,{0,11})

DRV_DEF_D(Sup,1,BootModeCtl,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x08000014)
DRV_DEF_F(Sup,1,BootModeCtl,cfgBootModeMask,2,{16,17})
DRV_DEF_F(Sup,1,BootModeCtl,cfgBootMode,2,{0,1})
DRV_DEF_F(Sup,1,BootModeCtl,cfgExtBootRstMask,1,{31,31})
DRV_DEF_F(Sup,1,BootModeCtl,cfgFormModeMask,3,{28,30})
DRV_DEF_F(Sup,1,BootModeCtl,cfgFormMode,3,{12,14})
DRV_DEF_F(Sup,1,BootModeCtl,cfgFuncModeMask,3,{24,26})
DRV_DEF_F(Sup,1,BootModeCtl,cfgFuncMode,3,{8,10})
DRV_DEF_F(Sup,1,BootModeCtl,cfgMemModeMask,3,{20,22})
DRV_DEF_F(Sup,1,BootModeCtl,cfgMemMode,3,{4,6})

DRV_DEF_D(Sup,1,BootStatus,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x0800001c)
DRV_DEF_F(Sup,1,BootStatus,xipBootDone,1,{0,0})

DRV_DEF_D(Sup,1,BootStrap,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x08000018)
DRV_DEF_F(Sup,1,BootStrap,bootModeLog,2,{16,17})
DRV_DEF_F(Sup,1,BootStrap,bootModePin,2,{0,1})
DRV_DEF_F(Sup,1,BootStrap,formModeLog,3,{28,30})
DRV_DEF_F(Sup,1,BootStrap,formModePin,3,{12,14})
DRV_DEF_F(Sup,1,BootStrap,funcModeLog,3,{24,26})
DRV_DEF_F(Sup,1,BootStrap,funcModePin,3,{8,10})
DRV_DEF_F(Sup,1,BootStrap,memModeLog,3,{20,22})
DRV_DEF_F(Sup,1,BootStrap,memModePin,3,{4,6})

DRV_DEF_SDK_D(Sup,1,ClkDivCfg,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x08000040)
DRV_DEF_SDK_F(Sup,1,ClkDivCfg,clkDivLed,8,{0,7})
DRV_DEF_SDK_F(Sup,1,ClkDivCfg,clkDivMdio,8,{8,15})

DRV_DEF_SDK_D(Sup,1,CpuMacMode,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x08000054)
DRV_DEF_SDK_F(Sup,1,CpuMacMode,modeECpu,1,{0,0})

DRV_DEF_D(Sup,1,DebugCfg,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x080000f0)
DRV_DEF_F(Sup,1,DebugCfg,cfgDebug,6,{0,5})
DRV_DEF_F(Sup,1,DebugCfg,cfgSysClkEn,1,{8,8})

DRV_DEF_SDK_D(Sup,1,DeviceId,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x080000b0)
DRV_DEF_SDK_F(Sup,1,DeviceId,devCode,4,{24,27})
DRV_DEF_SDK_F(Sup,1,DeviceId,devId,16,{0,15})
DRV_DEF_SDK_F(Sup,1,DeviceId,verId,4,{16,19})

DRV_DEF_SDK_D(Sup,1,EnClkCpuSub,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x080000a4)
DRV_DEF_SDK_F(Sup,1,EnClkCpuSub,cfgEnClkGpio,1,{9,9})
DRV_DEF_SDK_F(Sup,1,EnClkCpuSub,cfgEnClkLed,1,{10,10})
DRV_DEF_SDK_F(Sup,1,EnClkCpuSub,cfgEnClkMcu,1,{0,0})
DRV_DEF_SDK_F(Sup,1,EnClkCpuSub,cfgEnClkMdio,1,{11,11})
DRV_DEF_SDK_F(Sup,1,EnClkCpuSub,cfgEnClkQspi,1,{3,3})
DRV_DEF_SDK_F(Sup,1,EnClkCpuSub,cfgEnClkSysDma,1,{2,2})
DRV_DEF_SDK_F(Sup,1,EnClkCpuSub,cfgEnClkTimer,1,{8,8})
DRV_DEF_SDK_F(Sup,1,EnClkCpuSub,cfgEnClkUsi0,1,{4,4})
DRV_DEF_SDK_F(Sup,1,EnClkCpuSub,cfgEnClkUsi1,1,{5,5})
DRV_DEF_SDK_F(Sup,1,EnClkCpuSub,cfgEnClkUsi2,1,{6,6})
DRV_DEF_SDK_F(Sup,1,EnClkCpuSub,cfgEnClkWdt,1,{7,7})
DRV_DEF_SDK_F(Sup,1,EnClkCpuSub,enClkRegGlobal,1,{16,16})

DRV_DEF_SDK_D(Sup,1,EnClkSwitch,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x080000a8)
DRV_DEF_SDK_F(Sup,1,EnClkSwitch,cfgEnClkFxmii0,1,{8,8})
DRV_DEF_SDK_F(Sup,1,EnClkSwitch,cfgEnClkFxmii1,1,{9,9})
DRV_DEF_SDK_F(Sup,1,EnClkSwitch,cfgEnClkFxmii2,1,{10,10})
DRV_DEF_SDK_F(Sup,1,EnClkSwitch,cfgEnClkFxmii3,1,{11,11})
DRV_DEF_SDK_F(Sup,1,EnClkSwitch,cfgEnClkFxmii4,1,{12,12})
DRV_DEF_SDK_F(Sup,1,EnClkSwitch,cfgEnClkFxmii5,1,{13,13})
DRV_DEF_SDK_F(Sup,1,EnClkSwitch,cfgEnClkFxmii6,1,{14,14})
DRV_DEF_SDK_F(Sup,1,EnClkSwitch,cfgEnClkFxmii7,1,{15,15})
DRV_DEF_SDK_F(Sup,1,EnClkSwitch,cfgEnClkQsgmii0,1,{16,16})
DRV_DEF_SDK_F(Sup,1,EnClkSwitch,cfgEnClkQsgmii1,1,{17,17})
DRV_DEF_SDK_F(Sup,1,EnClkSwitch,cfgEnClkQsgmii2,1,{18,18})
DRV_DEF_SDK_F(Sup,1,EnClkSwitch,cfgEnClkQsgmii3,1,{19,19})
DRV_DEF_SDK_F(Sup,1,EnClkSwitch,cfgEnClkSgmii0,1,{0,0})
DRV_DEF_SDK_F(Sup,1,EnClkSwitch,cfgEnClkSgmii1,1,{1,1})
DRV_DEF_SDK_F(Sup,1,EnClkSwitch,cfgEnClkSgmii2,1,{2,2})
DRV_DEF_SDK_F(Sup,1,EnClkSwitch,cfgEnClkSgmii3,1,{3,3})
DRV_DEF_SDK_F(Sup,1,EnClkSwitch,cfgEnClkSgmii4,1,{4,4})
DRV_DEF_SDK_F(Sup,1,EnClkSwitch,cfgEnClkSgmii5,1,{5,5})
DRV_DEF_SDK_F(Sup,1,EnClkSwitch,cfgEnClkSgmii6,1,{6,6})
DRV_DEF_SDK_F(Sup,1,EnClkSwitch,cfgEnClkSgmii7,1,{7,7})

DRV_DEF_SDK_D(Sup,1,FxmiiMode,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x08000060)
DRV_DEF_SDK_F(Sup,1,FxmiiMode,modeFxmii,8,{0,7})

DRV_DEF_SDK_D(Sup,1,LedModeCtl,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x08000068)
DRV_DEF_SDK_F(Sup,1,LedModeCtl,cfgLedMode,1,{0,0})

DRV_DEF_D(Sup,1,McuDataBusMap,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x08000024)
DRV_DEF_F(Sup,1,McuDataBusMap,cfgDataBusBase,12,{0,11})
DRV_DEF_F(Sup,1,McuDataBusMap,cfgDataBusMask,12,{16,27})

DRV_DEF_D(Sup,1,McuDynFreqCfg,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x0800002c)
DRV_DEF_F(Sup,1,McuDynFreqCfg,cfgDynCpuFreqReq,1,{0,0})
DRV_DEF_F(Sup,1,McuDynFreqCfg,logDynCpuFreqAck,1,{4,4})

DRV_DEF_D(Sup,1,McuExtDbgReq,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x0800003c)
DRV_DEF_F(Sup,1,McuExtDbgReq,cfgExtDbgReq,1,{0,0})

DRV_DEF_D(Sup,1,McuExtIntr,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x08000034)
DRV_DEF_F(Sup,1,McuExtIntr,mcuExtIntr,1,{0,0})

DRV_DEF_D(Sup,1,McuInstBusMap,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x08000020)
DRV_DEF_F(Sup,1,McuInstBusMap,cfgInstBusBase,12,{0,11})
DRV_DEF_F(Sup,1,McuInstBusMap,cfgInstBusMask,12,{16,27})

DRV_DEF_D(Sup,1,McuIntrVecLog,0x0008,OP_DIRECT,TBL_SRAM,1,2,0x08000098)
DRV_DEF_F(Sup,1,McuIntrVecLog,intrVecLog,64,{0,63})

DRV_DEF_D(Sup,1,McuMCause,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x080000e0)
DRV_DEF_F(Sup,1,McuMCause,mcuMCause,32,{0,31})

DRV_DEF_D(Sup,1,McuMStatus,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x080000e4)
DRV_DEF_F(Sup,1,McuMStatus,mcuMStatus,32,{0,31})

DRV_DEF_D(Sup,1,McuMemCtl,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x08000044)
DRV_DEF_F(Sup,1,McuMemCtl,sysRamEccCorrectDis,1,{1,1})
DRV_DEF_F(Sup,1,McuMemCtl,sysRamEccDetectDis,1,{0,0})

DRV_DEF_D(Sup,1,McuMemInit,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x08000090)
DRV_DEF_F(Sup,1,McuMemInit,init,1,{0,0})

DRV_DEF_D(Sup,1,McuMemInitDone,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x08000094)
DRV_DEF_F(Sup,1,McuMemInitDone,initDone,1,{0,0})

DRV_DEF_D(Sup,1,McuMemStatus,0x0008,OP_DIRECT,TBL_SRAM,1,2,0x08000088)
DRV_DEF_F(Sup,1,McuMemStatus,sysRam0EccErrorAddr,14,{0,13})
DRV_DEF_F(Sup,1,McuMemStatus,sysRam0EccErrorValid,1,{15,15})
DRV_DEF_F(Sup,1,McuMemStatus,sysRam0EccSbeCnt,4,{32,35})
DRV_DEF_F(Sup,1,McuMemStatus,sysRam1EccErrorAddr,15,{16,30})
DRV_DEF_F(Sup,1,McuMemStatus,sysRam1EccErrorValid,1,{31,31})
DRV_DEF_F(Sup,1,McuMemStatus,sysRam1EccSbeCnt,4,{36,39})

DRV_DEF_D(Sup,1,McuMonStatus,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x08000084)
DRV_DEF_F(Sup,1,McuMonStatus,monMcuLockup,1,{0,0})
DRV_DEF_F(Sup,1,McuMonStatus,monMcuLpmdStatus,2,{4,5})
DRV_DEF_F(Sup,1,McuMonStatus,monMcuModeStatus,2,{8,9})

DRV_DEF_D(Sup,1,McuNmiIntr,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x08000030)
DRV_DEF_F(Sup,1,McuNmiIntr,cfgMcuLockupNmiEn,1,{1,1})
DRV_DEF_F(Sup,1,McuNmiIntr,mcuNmiIntr,1,{0,0})

DRV_DEF_D(Sup,1,McuResetAddr,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x08000028)
DRV_DEF_F(Sup,1,McuResetAddr,cfgResetAddr,32,{0,31})

DRV_DEF_D(Sup,1,McuRetirePc,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x08000080)
DRV_DEF_F(Sup,1,McuRetirePc,monMcuRetirePc,32,{0,31})

DRV_DEF_D(Sup,1,McuWakeupCtl,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x08000038)
DRV_DEF_F(Sup,1,McuWakeupCtl,mcuWakeup,1,{0,0})

DRV_DEF_D(Sup,1,PhyClkSel,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x08000004)
DRV_DEF_F(Sup,1,PhyClkSel,hssRxClkSel,8,{8,15})
DRV_DEF_F(Sup,1,PhyClkSel,hssTxClkSel,8,{0,7})
DRV_DEF_F(Sup,1,PhyClkSel,phyRxClkSel,8,{24,31})
DRV_DEF_F(Sup,1,PhyClkSel,phyTxClkSel,8,{16,23})
DRV_DEF_SDK_D(Sup,1,PowerMode,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x080000ac)
DRV_DEF_SDK_F(Sup,1,PowerMode,enableHss,8,{0,7})
DRV_DEF_SDK_F(Sup,1,PowerMode,enablePhy,8,{16,23})
DRV_DEF_SDK_F(Sup,1,PowerMode,tuneFineCdr,8,{8,15})

DRV_DEF_SDK_D(Sup,1,QsgmiiMode,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x08000058)
DRV_DEF_SDK_F(Sup,1,QsgmiiMode,modeQsgmii,4,{0,3})

DRV_DEF_D(Sup,1,QspiDivisor,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x08000050)
DRV_DEF_F(Sup,1,QspiDivisor,cfgQspiDivisor,10,{0,9})

DRV_DEF_D(Sup,1,QspiModeCfg,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x08000048)
DRV_DEF_F(Sup,1,QspiModeCfg,cfgQspiStrapMask,1,{4,4})
DRV_DEF_F(Sup,1,QspiModeCfg,cfgQspiXipEn,1,{0,0})

DRV_DEF_D(Sup,1,QspiPinMode,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x080000b4)
DRV_DEF_F(Sup,1,QspiPinMode,cfgQspiPinNum,2,{4,5})
DRV_DEF_F(Sup,1,QspiPinMode,cfgQspiPinSel,1,{0,0})
DRV_DEF_F(Sup,1,QspiPinMode,qspiModeLog,1,{8,8})

DRV_DEF_SDK_D(Sup,1,ResetCtlCpuSub,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x08000000)
DRV_DEF_SDK_F(Sup,1,ResetCtlCpuSub,cfgResetGpio,1,{10,10})
DRV_DEF_SDK_F(Sup,1,ResetCtlCpuSub,cfgResetLed,1,{11,11})
DRV_DEF_SDK_F(Sup,1,ResetCtlCpuSub,cfgResetMcuCore,1,{1,1})
DRV_DEF_SDK_F(Sup,1,ResetCtlCpuSub,cfgResetMcuHard,1,{0,0})
DRV_DEF_SDK_F(Sup,1,ResetCtlCpuSub,cfgResetMcuJtag,1,{2,2})
DRV_DEF_SDK_F(Sup,1,ResetCtlCpuSub,cfgResetMdio,1,{12,12})
DRV_DEF_SDK_F(Sup,1,ResetCtlCpuSub,cfgResetQspi,1,{3,3})
DRV_DEF_SDK_F(Sup,1,ResetCtlCpuSub,cfgResetSwitch,1,{16,16})
DRV_DEF_SDK_F(Sup,1,ResetCtlCpuSub,cfgResetSysDma,1,{7,7})
DRV_DEF_SDK_F(Sup,1,ResetCtlCpuSub,cfgResetTimer,1,{9,9})
DRV_DEF_SDK_F(Sup,1,ResetCtlCpuSub,cfgResetUsi0,1,{4,4})
DRV_DEF_SDK_F(Sup,1,ResetCtlCpuSub,cfgResetUsi1,1,{5,5})
DRV_DEF_SDK_F(Sup,1,ResetCtlCpuSub,cfgResetUsi2,1,{6,6})
DRV_DEF_SDK_F(Sup,1,ResetCtlCpuSub,cfgResetWdt,1,{8,8})

DRV_DEF_SDK_D(Sup,1,ResetCtlGmii,0x0008,OP_DIRECT,TBL_SRAM,1,2,0x08000008)
DRV_DEF_SDK_F(Sup,1,ResetCtlGmii,cfgResetCpuGmiiRx,1,{28,28})
DRV_DEF_SDK_F(Sup,1,ResetCtlGmii,cfgResetCpuGmiiTx,1,{60,60})
DRV_DEF_SDK_F(Sup,1,ResetCtlGmii,cfgResetGmii0Rx,1,{0,0})
DRV_DEF_SDK_F(Sup,1,ResetCtlGmii,cfgResetGmii0Tx,1,{32,32})
DRV_DEF_SDK_F(Sup,1,ResetCtlGmii,cfgResetGmii1Rx,1,{1,1})
DRV_DEF_SDK_F(Sup,1,ResetCtlGmii,cfgResetGmii1Tx,1,{33,33})
DRV_DEF_SDK_F(Sup,1,ResetCtlGmii,cfgResetGmii2Rx,1,{2,2})
DRV_DEF_SDK_F(Sup,1,ResetCtlGmii,cfgResetGmii2Tx,1,{34,34})
DRV_DEF_SDK_F(Sup,1,ResetCtlGmii,cfgResetGmii3Rx,1,{3,3})
DRV_DEF_SDK_F(Sup,1,ResetCtlGmii,cfgResetGmii3Tx,1,{35,35})
DRV_DEF_SDK_F(Sup,1,ResetCtlGmii,cfgResetGmii4Rx,1,{4,4})
DRV_DEF_SDK_F(Sup,1,ResetCtlGmii,cfgResetGmii4Tx,1,{36,36})
DRV_DEF_SDK_F(Sup,1,ResetCtlGmii,cfgResetGmii5Rx,1,{5,5})
DRV_DEF_SDK_F(Sup,1,ResetCtlGmii,cfgResetGmii5Tx,1,{37,37})
DRV_DEF_SDK_F(Sup,1,ResetCtlGmii,cfgResetGmii6Rx,1,{6,6})
DRV_DEF_SDK_F(Sup,1,ResetCtlGmii,cfgResetGmii6Tx,1,{38,38})
DRV_DEF_SDK_F(Sup,1,ResetCtlGmii,cfgResetGmii7Rx,1,{7,7})
DRV_DEF_SDK_F(Sup,1,ResetCtlGmii,cfgResetGmii7Tx,1,{39,39})
DRV_DEF_SDK_F(Sup,1,ResetCtlGmii,cfgResetGmii8Rx,1,{8,8})
DRV_DEF_SDK_F(Sup,1,ResetCtlGmii,cfgResetGmii8Tx,1,{40,40})
DRV_DEF_SDK_F(Sup,1,ResetCtlGmii,cfgResetGmii9Rx,1,{9,9})
DRV_DEF_SDK_F(Sup,1,ResetCtlGmii,cfgResetGmii9Tx,1,{41,41})
DRV_DEF_SDK_F(Sup,1,ResetCtlGmii,cfgResetGmii10Rx,1,{10,10})
DRV_DEF_SDK_F(Sup,1,ResetCtlGmii,cfgResetGmii10Tx,1,{42,42})
DRV_DEF_SDK_F(Sup,1,ResetCtlGmii,cfgResetGmii11Rx,1,{11,11})
DRV_DEF_SDK_F(Sup,1,ResetCtlGmii,cfgResetGmii11Tx,1,{43,43})
DRV_DEF_SDK_F(Sup,1,ResetCtlGmii,cfgResetGmii12Rx,1,{12,12})
DRV_DEF_SDK_F(Sup,1,ResetCtlGmii,cfgResetGmii12Tx,1,{44,44})
DRV_DEF_SDK_F(Sup,1,ResetCtlGmii,cfgResetGmii13Rx,1,{13,13})
DRV_DEF_SDK_F(Sup,1,ResetCtlGmii,cfgResetGmii13Tx,1,{45,45})
DRV_DEF_SDK_F(Sup,1,ResetCtlGmii,cfgResetGmii14Rx,1,{14,14})
DRV_DEF_SDK_F(Sup,1,ResetCtlGmii,cfgResetGmii14Tx,1,{46,46})
DRV_DEF_SDK_F(Sup,1,ResetCtlGmii,cfgResetGmii15Rx,1,{15,15})
DRV_DEF_SDK_F(Sup,1,ResetCtlGmii,cfgResetGmii15Tx,1,{47,47})
DRV_DEF_SDK_F(Sup,1,ResetCtlGmii,cfgResetGmii16Rx,1,{16,16})
DRV_DEF_SDK_F(Sup,1,ResetCtlGmii,cfgResetGmii16Tx,1,{48,48})
DRV_DEF_SDK_F(Sup,1,ResetCtlGmii,cfgResetGmii17Rx,1,{17,17})
DRV_DEF_SDK_F(Sup,1,ResetCtlGmii,cfgResetGmii17Tx,1,{49,49})
DRV_DEF_SDK_F(Sup,1,ResetCtlGmii,cfgResetGmii18Rx,1,{18,18})
DRV_DEF_SDK_F(Sup,1,ResetCtlGmii,cfgResetGmii18Tx,1,{50,50})
DRV_DEF_SDK_F(Sup,1,ResetCtlGmii,cfgResetGmii19Rx,1,{19,19})
DRV_DEF_SDK_F(Sup,1,ResetCtlGmii,cfgResetGmii19Tx,1,{51,51})
DRV_DEF_SDK_F(Sup,1,ResetCtlGmii,cfgResetGmii20Rx,1,{20,20})
DRV_DEF_SDK_F(Sup,1,ResetCtlGmii,cfgResetGmii20Tx,1,{52,52})
DRV_DEF_SDK_F(Sup,1,ResetCtlGmii,cfgResetGmii21Rx,1,{21,21})
DRV_DEF_SDK_F(Sup,1,ResetCtlGmii,cfgResetGmii21Tx,1,{53,53})
DRV_DEF_SDK_F(Sup,1,ResetCtlGmii,cfgResetGmii22Rx,1,{22,22})
DRV_DEF_SDK_F(Sup,1,ResetCtlGmii,cfgResetGmii22Tx,1,{54,54})
DRV_DEF_SDK_F(Sup,1,ResetCtlGmii,cfgResetGmii23Rx,1,{23,23})
DRV_DEF_SDK_F(Sup,1,ResetCtlGmii,cfgResetGmii23Tx,1,{55,55})
DRV_DEF_SDK_F(Sup,1,ResetCtlGmii,cfgResetGmii24Rx,1,{24,24})
DRV_DEF_SDK_F(Sup,1,ResetCtlGmii,cfgResetGmii24Tx,1,{56,56})
DRV_DEF_SDK_F(Sup,1,ResetCtlGmii,cfgResetGmii25Rx,1,{25,25})
DRV_DEF_SDK_F(Sup,1,ResetCtlGmii,cfgResetGmii25Tx,1,{57,57})
DRV_DEF_SDK_F(Sup,1,ResetCtlGmii,cfgResetGmii26Rx,1,{26,26})
DRV_DEF_SDK_F(Sup,1,ResetCtlGmii,cfgResetGmii26Tx,1,{58,58})
DRV_DEF_SDK_F(Sup,1,ResetCtlGmii,cfgResetGmii27Rx,1,{27,27})
DRV_DEF_SDK_F(Sup,1,ResetCtlGmii,cfgResetGmii27Tx,1,{59,59})

DRV_DEF_SDK_D(Sup,1,ResetCtlNet,0x0008,OP_DIRECT,TBL_SRAM,1,2,0x080000e8)
DRV_DEF_SDK_F(Sup,1,ResetCtlNet,cfgResetFxmii0Reg,1,{40,40})
DRV_DEF_SDK_F(Sup,1,ResetCtlNet,cfgResetFxmii0,1,{32,32})
DRV_DEF_SDK_F(Sup,1,ResetCtlNet,cfgResetFxmii1Reg,1,{41,41})
DRV_DEF_SDK_F(Sup,1,ResetCtlNet,cfgResetFxmii1,1,{33,33})
DRV_DEF_SDK_F(Sup,1,ResetCtlNet,cfgResetFxmii2Reg,1,{42,42})
DRV_DEF_SDK_F(Sup,1,ResetCtlNet,cfgResetFxmii2,1,{34,34})
DRV_DEF_SDK_F(Sup,1,ResetCtlNet,cfgResetFxmii3Reg,1,{43,43})
DRV_DEF_SDK_F(Sup,1,ResetCtlNet,cfgResetFxmii3,1,{35,35})
DRV_DEF_SDK_F(Sup,1,ResetCtlNet,cfgResetFxmii4Reg,1,{44,44})
DRV_DEF_SDK_F(Sup,1,ResetCtlNet,cfgResetFxmii4,1,{36,36})
DRV_DEF_SDK_F(Sup,1,ResetCtlNet,cfgResetFxmii5Reg,1,{45,45})
DRV_DEF_SDK_F(Sup,1,ResetCtlNet,cfgResetFxmii5,1,{37,37})
DRV_DEF_SDK_F(Sup,1,ResetCtlNet,cfgResetFxmii6Reg,1,{46,46})
DRV_DEF_SDK_F(Sup,1,ResetCtlNet,cfgResetFxmii6,1,{38,38})
DRV_DEF_SDK_F(Sup,1,ResetCtlNet,cfgResetFxmii7Reg,1,{47,47})
DRV_DEF_SDK_F(Sup,1,ResetCtlNet,cfgResetFxmii7,1,{39,39})
DRV_DEF_SDK_F(Sup,1,ResetCtlNet,cfgResetHss0,1,{2,2})
DRV_DEF_SDK_F(Sup,1,ResetCtlNet,cfgResetHss1,1,{3,3})
DRV_DEF_SDK_F(Sup,1,ResetCtlNet,cfgResetHss2,1,{4,4})
DRV_DEF_SDK_F(Sup,1,ResetCtlNet,cfgResetHss3,1,{5,5})
DRV_DEF_SDK_F(Sup,1,ResetCtlNet,cfgResetPhy0,1,{0,0})
DRV_DEF_SDK_F(Sup,1,ResetCtlNet,cfgResetPhy1,1,{1,1})
DRV_DEF_SDK_F(Sup,1,ResetCtlNet,cfgResetQsgmii0Reg,1,{28,28})
DRV_DEF_SDK_F(Sup,1,ResetCtlNet,cfgResetQsgmii0,1,{24,24})
DRV_DEF_SDK_F(Sup,1,ResetCtlNet,cfgResetQsgmii1Reg,1,{29,29})
DRV_DEF_SDK_F(Sup,1,ResetCtlNet,cfgResetQsgmii1,1,{25,25})
DRV_DEF_SDK_F(Sup,1,ResetCtlNet,cfgResetQsgmii2Reg,1,{30,30})
DRV_DEF_SDK_F(Sup,1,ResetCtlNet,cfgResetQsgmii2,1,{26,26})
DRV_DEF_SDK_F(Sup,1,ResetCtlNet,cfgResetQsgmii3Reg,1,{31,31})
DRV_DEF_SDK_F(Sup,1,ResetCtlNet,cfgResetQsgmii3,1,{27,27})
DRV_DEF_SDK_F(Sup,1,ResetCtlNet,cfgResetRgmii,1,{48,48})
DRV_DEF_SDK_F(Sup,1,ResetCtlNet,cfgResetSgmii0Reg,1,{16,16})
DRV_DEF_SDK_F(Sup,1,ResetCtlNet,cfgResetSgmii0,1,{8,8})
DRV_DEF_SDK_F(Sup,1,ResetCtlNet,cfgResetSgmii1Reg,1,{17,17})
DRV_DEF_SDK_F(Sup,1,ResetCtlNet,cfgResetSgmii1,1,{9,9})
DRV_DEF_SDK_F(Sup,1,ResetCtlNet,cfgResetSgmii2Reg,1,{18,18})
DRV_DEF_SDK_F(Sup,1,ResetCtlNet,cfgResetSgmii2,1,{10,10})
DRV_DEF_SDK_F(Sup,1,ResetCtlNet,cfgResetSgmii3Reg,1,{19,19})
DRV_DEF_SDK_F(Sup,1,ResetCtlNet,cfgResetSgmii3,1,{11,11})
DRV_DEF_SDK_F(Sup,1,ResetCtlNet,cfgResetSgmii4Reg,1,{20,20})
DRV_DEF_SDK_F(Sup,1,ResetCtlNet,cfgResetSgmii4,1,{12,12})
DRV_DEF_SDK_F(Sup,1,ResetCtlNet,cfgResetSgmii5Reg,1,{21,21})
DRV_DEF_SDK_F(Sup,1,ResetCtlNet,cfgResetSgmii5,1,{13,13})
DRV_DEF_SDK_F(Sup,1,ResetCtlNet,cfgResetSgmii6Reg,1,{22,22})
DRV_DEF_SDK_F(Sup,1,ResetCtlNet,cfgResetSgmii6,1,{14,14})
DRV_DEF_SDK_F(Sup,1,ResetCtlNet,cfgResetSgmii7Reg,1,{23,23})
DRV_DEF_SDK_F(Sup,1,ResetCtlNet,cfgResetSgmii7,1,{15,15})

DRV_DEF_SDK_D(Sup,1,RgmiiMode,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x08000064)
DRV_DEF_SDK_F(Sup,1,RgmiiMode,modeRgmiiV2,1,{4,4})
DRV_DEF_SDK_F(Sup,1,RgmiiMode,modeRgmii,1,{0,0})

DRV_DEF_SDK_D(Sup,1,SgmiiMode,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x0800005c)
DRV_DEF_SDK_F(Sup,1,SgmiiMode,modeSgmii,8,{0,7})

DRV_DEF_SDK_D(Sup,1,SyncECfg,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x080000a0)
DRV_DEF_SDK_F(Sup,1,SyncECfg,cfgOutEnA,1,{18,18})
DRV_DEF_SDK_F(Sup,1,SyncECfg,cfgOutEnB,1,{19,19})
DRV_DEF_SDK_F(Sup,1,SyncECfg,cfgSelFreqA,1,{16,16})
DRV_DEF_SDK_F(Sup,1,SyncECfg,cfgSelFreqB,1,{17,17})
DRV_DEF_SDK_F(Sup,1,SyncECfg,cfgSynceA,4,{0,3})
DRV_DEF_SDK_F(Sup,1,SyncECfg,cfgSynceB,4,{8,11})

DRV_DEF_D(Sup,1,WdtResetCfg,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x08000010)
DRV_DEF_F(Sup,1,WdtResetCfg,cfgWdt0RstBusEn,1,{4,4})
DRV_DEF_F(Sup,1,WdtResetCfg,cfgWdt0RstCoreEn,1,{1,1})
DRV_DEF_F(Sup,1,WdtResetCfg,cfgWdt0RstHardEn,1,{0,0})
DRV_DEF_F(Sup,1,WdtResetCfg,cfgWdt0RstPinDis,1,{7,7})
DRV_DEF_F(Sup,1,WdtResetCfg,cfgWdt0RstSupEn,1,{5,5})
DRV_DEF_F(Sup,1,WdtResetCfg,cfgWdt0RstWdtEn,1,{6,6})
DRV_DEF_F(Sup,1,WdtResetCfg,cfgWdt1RstBusEn,1,{8,8})
DRV_DEF_F(Sup,1,WdtResetCfg,cfgWdt1RstCoreEn,1,{3,3})
DRV_DEF_F(Sup,1,WdtResetCfg,cfgWdt1RstHardEn,1,{2,2})
DRV_DEF_F(Sup,1,WdtResetCfg,cfgWdt1RstPinDis,1,{11,11})
DRV_DEF_F(Sup,1,WdtResetCfg,cfgWdt1RstSupEn,1,{9,9})
DRV_DEF_F(Sup,1,WdtResetCfg,cfgWdt1RstWdtEn,1,{10,10})

DRV_DEF_D(Sup,1,SupInterruptNormal,0x0004,OP_DIRECT,TBL_SRAM,4,1,0x08000070)
DRV_DEF_F(Sup,1,SupInterruptNormal,regAckErrorEfuse,1,{5,5})
DRV_DEF_F(Sup,1,SupInterruptNormal,regAckErrorGpio,1,{2,2})
DRV_DEF_F(Sup,1,SupInterruptNormal,regAckErrorLed,1,{3,3})
DRV_DEF_F(Sup,1,SupInterruptNormal,regAckErrorMdio,1,{1,1})
DRV_DEF_F(Sup,1,SupInterruptNormal,regAckErrorNet,1,{4,4})
DRV_DEF_F(Sup,1,SupInterruptNormal,regAckErrorSup,1,{0,0})

DRV_DEF_SDK_D(Sup,1,SupPadIntr,0x0008,OP_DIRECT,TBL_SRAM,4,2,0x080000c0)
DRV_DEF_SDK_F(Sup,1,SupPadIntr,supPadIntrVec,64,{0,63})
DRV_DEF_SDK_D(Sup,1,SupPcsFuncIntr,0x0008,OP_DIRECT,TBL_SRAM,4,2,0x08000100)
DRV_DEF_SDK_F(Sup,1,SupPcsFuncIntr,fx0LinkDown,1,{49,49})
DRV_DEF_SDK_F(Sup,1,SupPcsFuncIntr,fx0LinkUp,1,{48,48})
DRV_DEF_SDK_F(Sup,1,SupPcsFuncIntr,fx1LinkDown,1,{51,51})
DRV_DEF_SDK_F(Sup,1,SupPcsFuncIntr,fx1LinkUp,1,{50,50})
DRV_DEF_SDK_F(Sup,1,SupPcsFuncIntr,fx2LinkDown,1,{53,53})
DRV_DEF_SDK_F(Sup,1,SupPcsFuncIntr,fx2LinkUp,1,{52,52})
DRV_DEF_SDK_F(Sup,1,SupPcsFuncIntr,fx3LinkDown,1,{54,54})
DRV_DEF_SDK_F(Sup,1,SupPcsFuncIntr,fx3LinkUp,1,{55,55})
DRV_DEF_SDK_F(Sup,1,SupPcsFuncIntr,fx4LinkDown,1,{56,56})
DRV_DEF_SDK_F(Sup,1,SupPcsFuncIntr,fx4LinkUp,1,{57,57})
DRV_DEF_SDK_F(Sup,1,SupPcsFuncIntr,fx5LinkDown,1,{58,58})
DRV_DEF_SDK_F(Sup,1,SupPcsFuncIntr,fx5LinkUp,1,{59,59})
DRV_DEF_SDK_F(Sup,1,SupPcsFuncIntr,fx6LinkDown,1,{60,60})
DRV_DEF_SDK_F(Sup,1,SupPcsFuncIntr,fx6LinkUp,1,{61,61})
DRV_DEF_SDK_F(Sup,1,SupPcsFuncIntr,fx7LinkDown,1,{62,62})
DRV_DEF_SDK_F(Sup,1,SupPcsFuncIntr,fx7LinkUp,1,{63,63})
DRV_DEF_SDK_F(Sup,1,SupPcsFuncIntr,qsgmii0LinkDown,1,{1,1})
DRV_DEF_SDK_F(Sup,1,SupPcsFuncIntr,qsgmii0LinkUp,1,{0,0})
DRV_DEF_SDK_F(Sup,1,SupPcsFuncIntr,qsgmii1LinkDown,1,{3,3})
DRV_DEF_SDK_F(Sup,1,SupPcsFuncIntr,qsgmii1LinkUp,1,{2,2})
DRV_DEF_SDK_F(Sup,1,SupPcsFuncIntr,qsgmii2LinkDown,1,{5,5})
DRV_DEF_SDK_F(Sup,1,SupPcsFuncIntr,qsgmii2LinkUp,1,{4,4})
DRV_DEF_SDK_F(Sup,1,SupPcsFuncIntr,qsgmii3LinkDown,1,{7,7})
DRV_DEF_SDK_F(Sup,1,SupPcsFuncIntr,qsgmii3LinkUp,1,{6,6})
DRV_DEF_SDK_F(Sup,1,SupPcsFuncIntr,qsgmii4LinkDown,1,{9,9})
DRV_DEF_SDK_F(Sup,1,SupPcsFuncIntr,qsgmii4LinkUp,1,{8,8})
DRV_DEF_SDK_F(Sup,1,SupPcsFuncIntr,qsgmii5LinkDown,1,{11,11})
DRV_DEF_SDK_F(Sup,1,SupPcsFuncIntr,qsgmii5LinkUp,1,{10,10})
DRV_DEF_SDK_F(Sup,1,SupPcsFuncIntr,qsgmii6LinkDown,1,{13,13})
DRV_DEF_SDK_F(Sup,1,SupPcsFuncIntr,qsgmii6LinkUp,1,{12,12})
DRV_DEF_SDK_F(Sup,1,SupPcsFuncIntr,qsgmii7LinkDown,1,{15,15})
DRV_DEF_SDK_F(Sup,1,SupPcsFuncIntr,qsgmii7LinkUp,1,{14,14})
DRV_DEF_SDK_F(Sup,1,SupPcsFuncIntr,qsgmii8LinkDown,1,{17,17})
DRV_DEF_SDK_F(Sup,1,SupPcsFuncIntr,qsgmii8LinkUp,1,{16,16})
DRV_DEF_SDK_F(Sup,1,SupPcsFuncIntr,qsgmii9LinkDown,1,{19,19})
DRV_DEF_SDK_F(Sup,1,SupPcsFuncIntr,qsgmii9LinkUp,1,{18,18})
DRV_DEF_SDK_F(Sup,1,SupPcsFuncIntr,qsgmii10LinkDown,1,{21,21})
DRV_DEF_SDK_F(Sup,1,SupPcsFuncIntr,qsgmii10LinkUp,1,{20,20})
DRV_DEF_SDK_F(Sup,1,SupPcsFuncIntr,qsgmii11LinkDown,1,{23,23})
DRV_DEF_SDK_F(Sup,1,SupPcsFuncIntr,qsgmii11LinkUp,1,{22,22})
DRV_DEF_SDK_F(Sup,1,SupPcsFuncIntr,qsgmii12LinkDown,1,{25,25})
DRV_DEF_SDK_F(Sup,1,SupPcsFuncIntr,qsgmii12LinkUp,1,{24,24})
DRV_DEF_SDK_F(Sup,1,SupPcsFuncIntr,qsgmii13LinkDown,1,{27,27})
DRV_DEF_SDK_F(Sup,1,SupPcsFuncIntr,qsgmii13LinkUp,1,{26,26})
DRV_DEF_SDK_F(Sup,1,SupPcsFuncIntr,qsgmii14LinkDown,1,{29,29})
DRV_DEF_SDK_F(Sup,1,SupPcsFuncIntr,qsgmii14LinkUp,1,{28,28})
DRV_DEF_SDK_F(Sup,1,SupPcsFuncIntr,qsgmii15LinkDown,1,{31,31})
DRV_DEF_SDK_F(Sup,1,SupPcsFuncIntr,qsgmii15LinkUp,1,{30,30})
DRV_DEF_SDK_F(Sup,1,SupPcsFuncIntr,sgmii0LinkDown,1,{33,33})
DRV_DEF_SDK_F(Sup,1,SupPcsFuncIntr,sgmii0LinkUp,1,{32,32})
DRV_DEF_SDK_F(Sup,1,SupPcsFuncIntr,sgmii1LinkDown,1,{35,35})
DRV_DEF_SDK_F(Sup,1,SupPcsFuncIntr,sgmii1LinkUp,1,{34,34})
DRV_DEF_SDK_F(Sup,1,SupPcsFuncIntr,sgmii2LinkDown,1,{37,37})
DRV_DEF_SDK_F(Sup,1,SupPcsFuncIntr,sgmii2LinkUp,1,{36,36})
DRV_DEF_SDK_F(Sup,1,SupPcsFuncIntr,sgmii3LinkDown,1,{39,39})
DRV_DEF_SDK_F(Sup,1,SupPcsFuncIntr,sgmii3LinkUp,1,{38,38})
DRV_DEF_SDK_F(Sup,1,SupPcsFuncIntr,sgmii4LinkDown,1,{41,41})
DRV_DEF_SDK_F(Sup,1,SupPcsFuncIntr,sgmii4LinkUp,1,{40,40})
DRV_DEF_SDK_F(Sup,1,SupPcsFuncIntr,sgmii5LinkDown,1,{43,43})
DRV_DEF_SDK_F(Sup,1,SupPcsFuncIntr,sgmii5LinkUp,1,{42,42})
DRV_DEF_SDK_F(Sup,1,SupPcsFuncIntr,sgmii6LinkDown,1,{45,45})
DRV_DEF_SDK_F(Sup,1,SupPcsFuncIntr,sgmii6LinkUp,1,{44,44})
DRV_DEF_SDK_F(Sup,1,SupPcsFuncIntr,sgmii7LinkDown,1,{47,47})
DRV_DEF_SDK_F(Sup,1,SupPcsFuncIntr,sgmii7LinkUp,1,{46,46})

//Version: 0.0.0.0
DRV_DEF_M(TimerSoc,1)
DRV_DEF_D(TimerSoc,1,Timer0ClkDivEn,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x0801081c)
DRV_DEF_F(TimerSoc,1,Timer0ClkDivEn,clkDivEn,1,{0,0})

DRV_DEF_D(TimerSoc,1,Timer0ClkDivNum,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x0801080c)
DRV_DEF_F(TimerSoc,1,Timer0ClkDivNum,clkDivNum,32,{0,31})

DRV_DEF_D(TimerSoc,1,Timer0Ctl,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x08010800)
DRV_DEF_F(TimerSoc,1,Timer0Ctl,cntEn,1,{0,0})
DRV_DEF_F(TimerSoc,1,Timer0Ctl,intrMask,1,{4,4})
DRV_DEF_F(TimerSoc,1,Timer0Ctl,loadMode,1,{3,3})
DRV_DEF_F(TimerSoc,1,Timer0Ctl,onceMode,1,{2,2})
DRV_DEF_F(TimerSoc,1,Timer0Ctl,udfMode,1,{1,1})

DRV_DEF_D(TimerSoc,1,Timer0CurValue,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x08010808)
DRV_DEF_F(TimerSoc,1,Timer0CurValue,curValue,32,{0,31})

DRV_DEF_D(TimerSoc,1,Timer0IntrClr,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x08010818)
DRV_DEF_F(TimerSoc,1,Timer0IntrClr,intrClr,1,{0,0})

DRV_DEF_D(TimerSoc,1,Timer0IntrRaw,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x08010810)
DRV_DEF_F(TimerSoc,1,Timer0IntrRaw,intrRawStatus,1,{0,0})

DRV_DEF_D(TimerSoc,1,Timer0IntrStatus,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x08010814)
DRV_DEF_F(TimerSoc,1,Timer0IntrStatus,intrOutStatus,1,{0,0})

DRV_DEF_D(TimerSoc,1,Timer0LoadValue,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x08010804)
DRV_DEF_F(TimerSoc,1,Timer0LoadValue,loadValue,32,{0,31})

DRV_DEF_D(TimerSoc,1,Timer1ClkDivEn,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x0801085c)
DRV_DEF_F(TimerSoc,1,Timer1ClkDivEn,clkDivEn,1,{0,0})

DRV_DEF_D(TimerSoc,1,Timer1ClkDivNum,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x0801084c)
DRV_DEF_F(TimerSoc,1,Timer1ClkDivNum,clkDivNum,32,{0,31})

DRV_DEF_D(TimerSoc,1,Timer1Ctl,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x08010840)
DRV_DEF_F(TimerSoc,1,Timer1Ctl,cntEn,1,{0,0})
DRV_DEF_F(TimerSoc,1,Timer1Ctl,intrMask,1,{4,4})
DRV_DEF_F(TimerSoc,1,Timer1Ctl,loadMode,1,{3,3})
DRV_DEF_F(TimerSoc,1,Timer1Ctl,onceMode,1,{2,2})
DRV_DEF_F(TimerSoc,1,Timer1Ctl,udfMode,1,{1,1})

DRV_DEF_D(TimerSoc,1,Timer1CurValue,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x08010848)
DRV_DEF_F(TimerSoc,1,Timer1CurValue,curValue,32,{0,31})

DRV_DEF_D(TimerSoc,1,Timer1IntrClr,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x08010858)
DRV_DEF_F(TimerSoc,1,Timer1IntrClr,intrClr,1,{0,0})

DRV_DEF_D(TimerSoc,1,Timer1IntrRaw,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x08010850)
DRV_DEF_F(TimerSoc,1,Timer1IntrRaw,intrRawStatus,1,{0,0})

DRV_DEF_D(TimerSoc,1,Timer1IntrStatus,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x08010854)
DRV_DEF_F(TimerSoc,1,Timer1IntrStatus,intrOutStatus,1,{0,0})

DRV_DEF_D(TimerSoc,1,Timer1LoadValue,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x08010844)
DRV_DEF_F(TimerSoc,1,Timer1LoadValue,loadValue,32,{0,31})

DRV_DEF_D(TimerSoc,1,TimerIntrStatus,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x08010890)
DRV_DEF_F(TimerSoc,1,TimerIntrStatus,intrVec,2,{0,1})

DRV_DEF_D(TimerSoc,1,TimerVersionId,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x08010880)
DRV_DEF_F(TimerSoc,1,TimerVersionId,verId,4,{0,3})

//Version: 0.0.0.0
DRV_DEF_M(WdtSoc,1)
DRV_DEF_D(WdtSoc,1,Wdt0ClkDivNum,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x08010c0c)
DRV_DEF_F(WdtSoc,1,Wdt0ClkDivNum,clkDivNum,32,{0,31})

DRV_DEF_D(WdtSoc,1,Wdt0Control,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x08010c00)
DRV_DEF_F(WdtSoc,1,Wdt0Control,cntEn,1,{0,0})
DRV_DEF_F(WdtSoc,1,Wdt0Control,intrEn,1,{1,1})
DRV_DEF_F(WdtSoc,1,Wdt0Control,resetEn,1,{2,2})

DRV_DEF_D(WdtSoc,1,Wdt0CurValue,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x08010c08)
DRV_DEF_F(WdtSoc,1,Wdt0CurValue,curValue,32,{0,31})

DRV_DEF_D(WdtSoc,1,Wdt0IntrClr,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x08010c18)
DRV_DEF_F(WdtSoc,1,Wdt0IntrClr,intrClr,1,{0,0})

DRV_DEF_D(WdtSoc,1,Wdt0IntrRaw,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x08010c10)
DRV_DEF_F(WdtSoc,1,Wdt0IntrRaw,intrRawStatus,1,{0,0})

DRV_DEF_D(WdtSoc,1,Wdt0IntrStatus,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x08010c14)
DRV_DEF_F(WdtSoc,1,Wdt0IntrStatus,intrOutStatus,1,{0,0})

DRV_DEF_D(WdtSoc,1,Wdt0LoadValue,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x08010c04)
DRV_DEF_F(WdtSoc,1,Wdt0LoadValue,loadValue,32,{0,31})

DRV_DEF_D(WdtSoc,1,Wdt1ClkDivNum,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x08010c4c)
DRV_DEF_F(WdtSoc,1,Wdt1ClkDivNum,clkDivNum,32,{0,31})

DRV_DEF_D(WdtSoc,1,Wdt1Control,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x08010c40)
DRV_DEF_F(WdtSoc,1,Wdt1Control,cntEn,1,{0,0})
DRV_DEF_F(WdtSoc,1,Wdt1Control,intrEn,1,{1,1})
DRV_DEF_F(WdtSoc,1,Wdt1Control,resetEn,1,{2,2})

DRV_DEF_D(WdtSoc,1,Wdt1CurValue,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x08010c48)
DRV_DEF_F(WdtSoc,1,Wdt1CurValue,curValue,32,{0,31})

DRV_DEF_D(WdtSoc,1,Wdt1IntrClr,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x08010c58)
DRV_DEF_F(WdtSoc,1,Wdt1IntrClr,intrClr,1,{0,0})

DRV_DEF_D(WdtSoc,1,Wdt1IntrRaw,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x08010c50)
DRV_DEF_F(WdtSoc,1,Wdt1IntrRaw,intrRawStatus,1,{0,0})

DRV_DEF_D(WdtSoc,1,Wdt1IntrStatus,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x08010c54)
DRV_DEF_F(WdtSoc,1,Wdt1IntrStatus,intrOutStatus,1,{0,0})

DRV_DEF_D(WdtSoc,1,Wdt1LoadValue,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x08010c44)
DRV_DEF_F(WdtSoc,1,Wdt1LoadValue,loadValue,32,{0,31})

DRV_DEF_D(WdtSoc,1,WdtCfgDisable,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x08010cf0)
DRV_DEF_F(WdtSoc,1,WdtCfgDisable,wdtCfgLock,1,{0,0})

DRV_DEF_D(WdtSoc,1,WdtIntrStatus,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x08010c90)
DRV_DEF_F(WdtSoc,1,WdtIntrStatus,wdtIntrVec,2,{0,1})

DRV_DEF_D(WdtSoc,1,WdtVersionId,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x08010c80)
DRV_DEF_F(WdtSoc,1,WdtVersionId,wdtVerId,4,{0,3})

DRV_DEF_M(AclMemBlk,1) // 00200000
DRV_DEF_SDK_D(AclMemBlk,1,AclKey,0x0020,OP_DIRECT,TBL_SRAM,256,6,0x00280000)
DRV_DEF_SDK_F(AclMemBlk,1,AclKey,data,164,{0,163})

DRV_DEF_D(AclMemBlk,1,KeyType0View0,0x0040,OP_DIRECT,TBL_SRAM,128,11,0x00200000)
DRV_DEF_F(AclMemBlk,1,KeyType0View0,valid,1,{330,330})
DRV_DEF_F(AclMemBlk,1,KeyType0View0,sportBitmap,29,{301,329})
DRV_DEF_F(AclMemBlk,1,KeyType0View0,tcpFlag,6,{295,300})
DRV_DEF_F(AclMemBlk,1,KeyType0View0,l4Dport,16,{279,294})
DRV_DEF_F(AclMemBlk,1,KeyType0View0,l4Sport,16,{263,278})
DRV_DEF_F(AclMemBlk,1,KeyType0View0,l4Vld,1,{262,262})
DRV_DEF_F(AclMemBlk,1,KeyType0View0,fragmentFlag,2,{260,261})
DRV_DEF_F(AclMemBlk,1,KeyType0View0,tos,8,{252,259})
DRV_DEF_F(AclMemBlk,1,KeyType0View0,ipProtocol,8,{244,251})
DRV_DEF_F(AclMemBlk,1,KeyType0View0,dip,32,{212,243})
DRV_DEF_F(AclMemBlk,1,KeyType0View0,sip,32,{180,211})
DRV_DEF_F(AclMemBlk,1,KeyType0View0,ipVld,1,{179,179})
DRV_DEF_F(AclMemBlk,1,KeyType0View0,ethtype,16,{163,178})
DRV_DEF_F(AclMemBlk,1,KeyType0View0,ctagStatus,2,{161,162})
DRV_DEF_F(AclMemBlk,1,KeyType0View0,stagStatus,2,{159,160})
DRV_DEF_F(AclMemBlk,1,KeyType0View0,ctag,16,{143,158})
DRV_DEF_F(AclMemBlk,1,KeyType0View0,stag,16,{127,142})
DRV_DEF_F(AclMemBlk,1,KeyType0View0,sa,48,{79,126})
DRV_DEF_F(AclMemBlk,1,KeyType0View0,da,48,{31,78})
DRV_DEF_F(AclMemBlk,1,KeyType0View0,rsv,31,{0,30})

DRV_DEF_D(AclMemBlk,1,KeyType0View1,0x0040,OP_DIRECT,TBL_SRAM,128,11,0x00200000)
DRV_DEF_F(AclMemBlk,1,KeyType0View1,valid,1,{330,330})
DRV_DEF_F(AclMemBlk,1,KeyType0View1,sportBitmap,29,{301,329})
DRV_DEF_F(AclMemBlk,1,KeyType0View1,reserved0,9,{292,300})
DRV_DEF_F(AclMemBlk,1,KeyType0View1,l2Payload,112,{180,291})
DRV_DEF_F(AclMemBlk,1,KeyType0View1,ipVld,1,{179,179})
DRV_DEF_F(AclMemBlk,1,KeyType0View1,ethtype,16,{163,178})
DRV_DEF_F(AclMemBlk,1,KeyType0View1,ctagStatus,2,{161,162})
DRV_DEF_F(AclMemBlk,1,KeyType0View1,stagStatus,2,{159,160})
DRV_DEF_F(AclMemBlk,1,KeyType0View1,ctag,16,{143,158})
DRV_DEF_F(AclMemBlk,1,KeyType0View1,stag,16,{127,142})
DRV_DEF_F(AclMemBlk,1,KeyType0View1,sa,48,{79,126})
DRV_DEF_F(AclMemBlk,1,KeyType0View1,da,48,{31,78})
DRV_DEF_F(AclMemBlk,1,KeyType0View1,rsv,31,{0,30})

DRV_DEF_D(AclMemBlk,1,KeyType1View0,0x0040,OP_DIRECT,TBL_SRAM,128,11,0x00200000)
DRV_DEF_F(AclMemBlk,1,KeyType1View0,valid,1,{330,330})
DRV_DEF_F(AclMemBlk,1,KeyType1View0,sportBitmap,29,{301,329})
DRV_DEF_F(AclMemBlk,1,KeyType1View0,reserved0,13,{288,300})
DRV_DEF_F(AclMemBlk,1,KeyType1View0,ipVld,1,{287,287})
DRV_DEF_F(AclMemBlk,1,KeyType1View0,dip,128,{159,286})
DRV_DEF_F(AclMemBlk,1,KeyType1View0,sip,128,{31,158})
DRV_DEF_F(AclMemBlk,1,KeyType1View0,rsv,31,{0,30})

DRV_DEF_D(AclMemBlk,1,KeyType2View0,0x0040,OP_DIRECT,TBL_SRAM,128,11,0x00200000)
DRV_DEF_F(AclMemBlk,1,KeyType2View0,valid,1,{330,330})
DRV_DEF_F(AclMemBlk,1,KeyType2View0,sportBitmap,29,{301,329})
DRV_DEF_F(AclMemBlk,1,KeyType2View0,reserved0,2,{299,300})
DRV_DEF_F(AclMemBlk,1,KeyType2View0,udfValid,8,{291,298})
DRV_DEF_F(AclMemBlk,1,KeyType2View0,udfType,4,{287,290})
DRV_DEF_F(AclMemBlk,1,KeyType2View0,udf,256,{31,286})
DRV_DEF_F(AclMemBlk,1,KeyType2View0,rsv,31,{0,30})

DRV_DEF_SDK_D(AclMemBlk,1,Key160MacView0,0x0040,OP_DIRECT,TBL_SRAM_MASK,128,6,0x00280000)
DRV_DEF_SDK_F(AclMemBlk,1,Key160MacView0,valid,1,{163,163})
DRV_DEF_SDK_F(AclMemBlk,1,Key160MacView0,keyType,4,{159,162})
DRV_DEF_SDK_F(AclMemBlk,1,Key160MacView0,sportBitmap,14,{145,158})
DRV_DEF_SDK_F(AclMemBlk,1,Key160MacView0,portType,2,{143,144})
DRV_DEF_SDK_F(AclMemBlk,1,Key160MacView0,ethtype,16,{127,142})
DRV_DEF_SDK_F(AclMemBlk,1,Key160MacView0,stagStatus,1,{126,126})
DRV_DEF_SDK_F(AclMemBlk,1,Key160MacView0,stag,16,{110,125})
DRV_DEF_SDK_F(AclMemBlk,1,Key160MacView0,sa,48,{62,109})
DRV_DEF_SDK_F(AclMemBlk,1,Key160MacView0,da,48,{14,61})
DRV_DEF_SDK_F(AclMemBlk,1,Key160MacView0,rangeBitmap,12,{2,13})
DRV_DEF_SDK_F(AclMemBlk,1,Key160MacView0,reserved0,2,{0,1})

DRV_DEF_SDK_D(AclMemBlk,1,Key160MacudfView0,0x0040,OP_DIRECT,TBL_SRAM_MASK,128,6,0x00280000)
DRV_DEF_SDK_F(AclMemBlk,1,Key160MacudfView0,valid,1,{163,163})
DRV_DEF_SDK_F(AclMemBlk,1,Key160MacudfView0,keyType,4,{159,162})
DRV_DEF_SDK_F(AclMemBlk,1,Key160MacudfView0,sportBitmap,14,{145,158})
DRV_DEF_SDK_F(AclMemBlk,1,Key160MacudfView0,portType,2,{143,144})
DRV_DEF_SDK_F(AclMemBlk,1,Key160MacudfView0,ethtype,16,{127,142})
DRV_DEF_SDK_F(AclMemBlk,1,Key160MacudfView0,macAddr,48,{79,126})
DRV_DEF_SDK_F(AclMemBlk,1,Key160MacudfView0,isDa,1,{78,78})
DRV_DEF_SDK_F(AclMemBlk,1,Key160MacudfView0,l4Type,3,{75,77})
DRV_DEF_SDK_F(AclMemBlk,1,Key160MacudfView0,l3Type,3,{72,74})
DRV_DEF_SDK_F(AclMemBlk,1,Key160MacudfView0,l2Type,2,{70,71})
DRV_DEF_SDK_F(AclMemBlk,1,Key160MacudfView0,udfIndex,3,{67,69})
DRV_DEF_SDK_F(AclMemBlk,1,Key160MacudfView0,udf01Valid,2,{65,66})
DRV_DEF_SDK_F(AclMemBlk,1,Key160MacudfView0,udf1,32,{33,64})
DRV_DEF_SDK_F(AclMemBlk,1,Key160MacudfView0,udf0,32,{1,32})
DRV_DEF_SDK_F(AclMemBlk,1,Key160MacudfView0,reserved0,1,{0,0})

DRV_DEF_SDK_D(AclMemBlk,1,Key160EthudfView0,0x0040,OP_DIRECT,TBL_SRAM_MASK,128,6,0x00280000)
DRV_DEF_SDK_F(AclMemBlk,1,Key160EthudfView0,valid,1,{163,163})
DRV_DEF_SDK_F(AclMemBlk,1,Key160EthudfView0,keyType,4,{159,162})
DRV_DEF_SDK_F(AclMemBlk,1,Key160EthudfView0,sportBitmap,14,{145,158})
DRV_DEF_SDK_F(AclMemBlk,1,Key160EthudfView0,portType,2,{143,144})
DRV_DEF_SDK_F(AclMemBlk,1,Key160EthudfView0,l4Type,3,{140,142})
DRV_DEF_SDK_F(AclMemBlk,1,Key160EthudfView0,l3Type,3,{137,139})
DRV_DEF_SDK_F(AclMemBlk,1,Key160EthudfView0,l2Type,2,{135,136})
DRV_DEF_SDK_F(AclMemBlk,1,Key160EthudfView0,udfIndex,3,{132,134})
DRV_DEF_SDK_F(AclMemBlk,1,Key160EthudfView0,udfValid,4,{128,131})
DRV_DEF_SDK_F(AclMemBlk,1,Key160EthudfView0,udf3,32,{96,127})
DRV_DEF_SDK_F(AclMemBlk,1,Key160EthudfView0,udf2,32,{64,95})
DRV_DEF_SDK_F(AclMemBlk,1,Key160EthudfView0,udf1,32,{32,63})
DRV_DEF_SDK_F(AclMemBlk,1,Key160EthudfView0,udf0,32,{0,31})

DRV_DEF_SDK_D(AclMemBlk,1,Key320MacipudfView0,0x0040,OP_DIRECT,TBL_SRAM_MASK,128,14,0x00280000)
DRV_DEF_SDK_F(AclMemBlk,1,Key320MacipudfView0,valid,1,{419,419})
DRV_DEF_SDK_F(AclMemBlk,1,Key320MacipudfView0,keyType,4,{415,418})
DRV_DEF_SDK_F(AclMemBlk,1,Key320MacipudfView0,sportBitmap,14,{401,414})
DRV_DEF_SDK_F(AclMemBlk,1,Key320MacipudfView0,portType,2,{399,400})
DRV_DEF_SDK_F(AclMemBlk,1,Key320MacipudfView0,l4Dport,16,{383,398})
DRV_DEF_SDK_F(AclMemBlk,1,Key320MacipudfView0,l4Sport,16,{367,382})
DRV_DEF_SDK_F(AclMemBlk,1,Key320MacipudfView0,tcpFlag,6,{361,366})
DRV_DEF_SDK_F(AclMemBlk,1,Key320MacipudfView0,l4Type,3,{358,360})
DRV_DEF_SDK_F(AclMemBlk,1,Key320MacipudfView0,fragmentFlag,2,{356,357})
DRV_DEF_SDK_F(AclMemBlk,1,Key320MacipudfView0,ipOption,1,{355,355})
DRV_DEF_SDK_F(AclMemBlk,1,Key320MacipudfView0,tos,8,{347,354})
DRV_DEF_SDK_F(AclMemBlk,1,Key320MacipudfView0,ipProtocol,8,{339,346})
DRV_DEF_SDK_F(AclMemBlk,1,Key320MacipudfView0,dip,32,{307,338})
DRV_DEF_SDK_F(AclMemBlk,1,Key320MacipudfView0,sip,32,{275,306})
DRV_DEF_SDK_F(AclMemBlk,1,Key320MacipudfView0,l3Type,3,{272,274})
DRV_DEF_SDK_F(AclMemBlk,1,Key320MacipudfView0,stagStatus,1,{271,271})
DRV_DEF_SDK_F(AclMemBlk,1,Key320MacipudfView0,svid,12,{259,270})
DRV_DEF_SDK_F(AclMemBlk,1,Key320MacipudfView0,sa1,3,{256,258})
DRV_DEF_SDK_F(AclMemBlk,1,Key320MacipudfView0,padding0,92,{164,255})
DRV_DEF_SDK_F(AclMemBlk,1,Key320MacipudfView0,valid0,1,{163,163})
DRV_DEF_SDK_F(AclMemBlk,1,Key320MacipudfView0,sa0,45,{118,162})
DRV_DEF_SDK_F(AclMemBlk,1,Key320MacipudfView0,da,48,{70,117})
DRV_DEF_SDK_F(AclMemBlk,1,Key320MacipudfView0,udfIndex,3,{67,69})
DRV_DEF_SDK_F(AclMemBlk,1,Key320MacipudfView0,udf01Valid,2,{65,66})
DRV_DEF_SDK_F(AclMemBlk,1,Key320MacipudfView0,udf1,32,{33,64})
DRV_DEF_SDK_F(AclMemBlk,1,Key320MacipudfView0,udf0,32,{1,32})
DRV_DEF_SDK_F(AclMemBlk,1,Key320MacipudfView0,ctagStatus,1,{0,0})

DRV_DEF_SDK_D(AclMemBlk,1,Key160IpView0,0x0040,OP_DIRECT,TBL_SRAM_MASK,128,6,0x00280000)
DRV_DEF_SDK_F(AclMemBlk,1,Key160IpView0,valid,1,{163,163})
DRV_DEF_SDK_F(AclMemBlk,1,Key160IpView0,keyType,4,{159,162})
DRV_DEF_SDK_F(AclMemBlk,1,Key160IpView0,sportBitmap,14,{145,158})
DRV_DEF_SDK_F(AclMemBlk,1,Key160IpView0,portType,2,{143,144})
DRV_DEF_SDK_F(AclMemBlk,1,Key160IpView0,l4Dport,16,{127,142})
DRV_DEF_SDK_F(AclMemBlk,1,Key160IpView0,l4Sport,16,{111,126})
DRV_DEF_SDK_F(AclMemBlk,1,Key160IpView0,tcpFlag,6,{105,110})
DRV_DEF_SDK_F(AclMemBlk,1,Key160IpView0,l4Type,3,{102,104})
DRV_DEF_SDK_F(AclMemBlk,1,Key160IpView0,fragmentFlag,2,{100,101})
DRV_DEF_SDK_F(AclMemBlk,1,Key160IpView0,ipOption,1,{99,99})
DRV_DEF_SDK_F(AclMemBlk,1,Key160IpView0,tos,8,{91,98})
DRV_DEF_SDK_F(AclMemBlk,1,Key160IpView0,ipProtocol,8,{83,90})
DRV_DEF_SDK_F(AclMemBlk,1,Key160IpView0,dip,32,{51,82})
DRV_DEF_SDK_F(AclMemBlk,1,Key160IpView0,sip,32,{19,50})
DRV_DEF_SDK_F(AclMemBlk,1,Key160IpView0,l3Type,3,{16,18})
DRV_DEF_SDK_F(AclMemBlk,1,Key160IpView0,rangeBitmap,12,{4,15})
DRV_DEF_SDK_F(AclMemBlk,1,Key160IpView0,reserved0,4,{0,3})

DRV_DEF_SDK_D(AclMemBlk,1,Key320IpudfView0,0x0040,OP_DIRECT,TBL_SRAM_MASK,128,14,0x00280000)
DRV_DEF_SDK_F(AclMemBlk,1,Key320IpudfView0,valid,1,{419,419})
DRV_DEF_SDK_F(AclMemBlk,1,Key320IpudfView0,keyType,4,{415,418})
DRV_DEF_SDK_F(AclMemBlk,1,Key320IpudfView0,sportBitmap,14,{401,414})
DRV_DEF_SDK_F(AclMemBlk,1,Key320IpudfView0,portType,2,{399,400})
DRV_DEF_SDK_F(AclMemBlk,1,Key320IpudfView0,l4Dport,16,{383,398})
DRV_DEF_SDK_F(AclMemBlk,1,Key320IpudfView0,l4Sport,16,{367,382})
DRV_DEF_SDK_F(AclMemBlk,1,Key320IpudfView0,tcpFlag,6,{361,366})
DRV_DEF_SDK_F(AclMemBlk,1,Key320IpudfView0,l4Type,3,{358,360})
DRV_DEF_SDK_F(AclMemBlk,1,Key320IpudfView0,fragmentFlag,2,{356,357})
DRV_DEF_SDK_F(AclMemBlk,1,Key320IpudfView0,ipOption,1,{355,355})
DRV_DEF_SDK_F(AclMemBlk,1,Key320IpudfView0,tos,8,{347,354})
DRV_DEF_SDK_F(AclMemBlk,1,Key320IpudfView0,ipProtocol,8,{339,346})
DRV_DEF_SDK_F(AclMemBlk,1,Key320IpudfView0,dip,32,{307,338})
DRV_DEF_SDK_F(AclMemBlk,1,Key320IpudfView0,sip,32,{275,306})
DRV_DEF_SDK_F(AclMemBlk,1,Key320IpudfView0,l3Type,3,{272,274})
DRV_DEF_SDK_F(AclMemBlk,1,Key320IpudfView0,ethtype,16,{256,271})
DRV_DEF_SDK_F(AclMemBlk,1,Key320IpudfView0,padding0,92,{164,255})
DRV_DEF_SDK_F(AclMemBlk,1,Key320IpudfView0,valid0,1,{163,163})
DRV_DEF_SDK_F(AclMemBlk,1,Key320IpudfView0,stagStatus,1,{162,162})
DRV_DEF_SDK_F(AclMemBlk,1,Key320IpudfView0,svid,12,{150,161})
DRV_DEF_SDK_F(AclMemBlk,1,Key320IpudfView0,rangeBitmap,12,{138,149})
DRV_DEF_SDK_F(AclMemBlk,1,Key320IpudfView0,udfIndex,3,{135,137})
DRV_DEF_SDK_F(AclMemBlk,1,Key320IpudfView0,udfValid,4,{131,134})
DRV_DEF_SDK_F(AclMemBlk,1,Key320IpudfView0,udf3,32,{99,130})
DRV_DEF_SDK_F(AclMemBlk,1,Key320IpudfView0,udf2,32,{67,98})
DRV_DEF_SDK_F(AclMemBlk,1,Key320IpudfView0,udf1,32,{35,66})
DRV_DEF_SDK_F(AclMemBlk,1,Key320IpudfView0,udf0,32,{3,34})
DRV_DEF_SDK_F(AclMemBlk,1,Key320IpudfView0,ctagStatus,1,{2,2})
DRV_DEF_SDK_F(AclMemBlk,1,Key320IpudfView0,reserved0,2,{0,1})

DRV_DEF_SDK_D(AclMemBlk,1,Key640Macipv6View0,0x0040,OP_DIRECT,TBL_SRAM_MASK,128,14,0x00280000)
DRV_DEF_SDK_F(AclMemBlk,1,Key640Macipv6View0,valid,1,{419,419})
DRV_DEF_SDK_F(AclMemBlk,1,Key640Macipv6View0,keyType,4,{415,418})
DRV_DEF_SDK_F(AclMemBlk,1,Key640Macipv6View0,sportBitmap,14,{401,414})
DRV_DEF_SDK_F(AclMemBlk,1,Key640Macipv6View0,portType,2,{399,400})
DRV_DEF_SDK_F(AclMemBlk,1,Key640Macipv6View0,l4Dport,16,{383,398})
DRV_DEF_SDK_F(AclMemBlk,1,Key640Macipv6View0,l4Sport,16,{367,382})
DRV_DEF_SDK_F(AclMemBlk,1,Key640Macipv6View0,tcpFlag,6,{361,366})
DRV_DEF_SDK_F(AclMemBlk,1,Key640Macipv6View0,l4Type,3,{358,360})
DRV_DEF_SDK_F(AclMemBlk,1,Key640Macipv6View0,fragmentFlag,2,{356,357})
DRV_DEF_SDK_F(AclMemBlk,1,Key640Macipv6View0,ipOption,1,{355,355})
DRV_DEF_SDK_F(AclMemBlk,1,Key640Macipv6View0,tos,8,{347,354})
DRV_DEF_SDK_F(AclMemBlk,1,Key640Macipv6View0,ipProtocol,8,{339,346})
DRV_DEF_SDK_F(AclMemBlk,1,Key640Macipv6View0,l3Type,3,{336,338})
DRV_DEF_SDK_F(AclMemBlk,1,Key640Macipv6View0,ipaddr2,64,{272,335})
DRV_DEF_SDK_F(AclMemBlk,1,Key640Macipv6View0,ipaddr11,16,{256,271})
DRV_DEF_SDK_F(AclMemBlk,1,Key640Macipv6View0,padding0,92,{164,255})
DRV_DEF_SDK_F(AclMemBlk,1,Key640Macipv6View0,valid0,1,{163,163})
DRV_DEF_SDK_F(AclMemBlk,1,Key640Macipv6View0,ipaddr10,48,{115,162})
DRV_DEF_SDK_F(AclMemBlk,1,Key640Macipv6View0,ctagStatus,1,{114,114})
DRV_DEF_SDK_F(AclMemBlk,1,Key640Macipv6View0,stagStatus,1,{113,113})
DRV_DEF_SDK_F(AclMemBlk,1,Key640Macipv6View0,stag,16,{97,112})
DRV_DEF_SDK_F(AclMemBlk,1,Key640Macipv6View0,sa,48,{49,96})
DRV_DEF_SDK_F(AclMemBlk,1,Key640Macipv6View0,da,48,{1,48})
DRV_DEF_SDK_F(AclMemBlk,1,Key640Macipv6View0,reserved0,1,{0,0})

DRV_DEF_SDK_D(AclMemBlk,1,Key320Ipv6View0,0x0040,OP_DIRECT,TBL_SRAM_MASK,128,14,0x00280000)
DRV_DEF_SDK_F(AclMemBlk,1,Key320Ipv6View0,valid,1,{419,419})
DRV_DEF_SDK_F(AclMemBlk,1,Key320Ipv6View0,keyType,4,{415,418})
DRV_DEF_SDK_F(AclMemBlk,1,Key320Ipv6View0,sportBitmap,14,{401,414})
DRV_DEF_SDK_F(AclMemBlk,1,Key320Ipv6View0,portType,2,{399,400})
DRV_DEF_SDK_F(AclMemBlk,1,Key320Ipv6View0,l4Sport,16,{383,398})
DRV_DEF_SDK_F(AclMemBlk,1,Key320Ipv6View0,tcpFlag,6,{377,382})
DRV_DEF_SDK_F(AclMemBlk,1,Key320Ipv6View0,l4Type,3,{374,376})
DRV_DEF_SDK_F(AclMemBlk,1,Key320Ipv6View0,fragmentFlag,2,{372,373})
DRV_DEF_SDK_F(AclMemBlk,1,Key320Ipv6View0,ipOption,1,{371,371})
DRV_DEF_SDK_F(AclMemBlk,1,Key320Ipv6View0,tos,8,{363,370})
DRV_DEF_SDK_F(AclMemBlk,1,Key320Ipv6View0,ipProtocol,8,{355,362})
DRV_DEF_SDK_F(AclMemBlk,1,Key320Ipv6View0,l3Type,3,{352,354})
DRV_DEF_SDK_F(AclMemBlk,1,Key320Ipv6View0,dip1,96,{256,351})
DRV_DEF_SDK_F(AclMemBlk,1,Key320Ipv6View0,padding0,92,{164,255})
DRV_DEF_SDK_F(AclMemBlk,1,Key320Ipv6View0,valid0,1,{163,163})
DRV_DEF_SDK_F(AclMemBlk,1,Key320Ipv6View0,dip0,32,{131,162})
DRV_DEF_SDK_F(AclMemBlk,1,Key320Ipv6View0,sip,128,{3,130})
DRV_DEF_SDK_F(AclMemBlk,1,Key320Ipv6View0,reserved0,3,{0,2})

DRV_DEF_SDK_D(AclMemBlk,1,Key640Macipv6udfView0,0x0080,OP_DIRECT,TBL_SRAM_MASK,128,30,0x00280000)
DRV_DEF_SDK_F(AclMemBlk,1,Key640Macipv6udfView0,valid,1,{931,931})
DRV_DEF_SDK_F(AclMemBlk,1,Key640Macipv6udfView0,keyType,4,{927,930})
DRV_DEF_SDK_F(AclMemBlk,1,Key640Macipv6udfView0,sportBitmap,14,{913,926})
DRV_DEF_SDK_F(AclMemBlk,1,Key640Macipv6udfView0,portType,2,{911,912})
DRV_DEF_SDK_F(AclMemBlk,1,Key640Macipv6udfView0,l4Dport,16,{895,910})
DRV_DEF_SDK_F(AclMemBlk,1,Key640Macipv6udfView0,l4Sport,16,{879,894})
DRV_DEF_SDK_F(AclMemBlk,1,Key640Macipv6udfView0,tcpFlag,6,{873,878})
DRV_DEF_SDK_F(AclMemBlk,1,Key640Macipv6udfView0,l4Type,3,{870,872})
DRV_DEF_SDK_F(AclMemBlk,1,Key640Macipv6udfView0,fragmentFlag,2,{868,869})
DRV_DEF_SDK_F(AclMemBlk,1,Key640Macipv6udfView0,ipOption,1,{867,867})
DRV_DEF_SDK_F(AclMemBlk,1,Key640Macipv6udfView0,tos,8,{859,866})
DRV_DEF_SDK_F(AclMemBlk,1,Key640Macipv6udfView0,ipProtocol,8,{851,858})
DRV_DEF_SDK_F(AclMemBlk,1,Key640Macipv6udfView0,l3Type,3,{848,850})
DRV_DEF_SDK_F(AclMemBlk,1,Key640Macipv6udfView0,dip1,80,{768,847})
DRV_DEF_SDK_F(AclMemBlk,1,Key640Macipv6udfView0,padding2,92,{676,767})
DRV_DEF_SDK_F(AclMemBlk,1,Key640Macipv6udfView0,valid2,1,{675,675})
DRV_DEF_SDK_F(AclMemBlk,1,Key640Macipv6udfView0,dip0,48,{627,674})
DRV_DEF_SDK_F(AclMemBlk,1,Key640Macipv6udfView0,sip1,115,{512,626})
DRV_DEF_SDK_F(AclMemBlk,1,Key640Macipv6udfView0,padding1,92,{420,511})
DRV_DEF_SDK_F(AclMemBlk,1,Key640Macipv6udfView0,valid1,1,{419,419})
DRV_DEF_SDK_F(AclMemBlk,1,Key640Macipv6udfView0,sip0,13,{406,418})
DRV_DEF_SDK_F(AclMemBlk,1,Key640Macipv6udfView0,ethtype,16,{390,405})
DRV_DEF_SDK_F(AclMemBlk,1,Key640Macipv6udfView0,ctagStatus,1,{389,389})
DRV_DEF_SDK_F(AclMemBlk,1,Key640Macipv6udfView0,stagStatus,1,{388,388})
DRV_DEF_SDK_F(AclMemBlk,1,Key640Macipv6udfView0,ctag,16,{372,387})
DRV_DEF_SDK_F(AclMemBlk,1,Key640Macipv6udfView0,stag,16,{356,371})
DRV_DEF_SDK_F(AclMemBlk,1,Key640Macipv6udfView0,sa,48,{308,355})
DRV_DEF_SDK_F(AclMemBlk,1,Key640Macipv6udfView0,da,48,{260,307})
DRV_DEF_SDK_F(AclMemBlk,1,Key640Macipv6udfView0,rangeBitmap,4,{256,259})
DRV_DEF_SDK_F(AclMemBlk,1,Key640Macipv6udfView0,padding0,92,{164,255})
DRV_DEF_SDK_F(AclMemBlk,1,Key640Macipv6udfView0,valid0,1,{163,163})
DRV_DEF_SDK_F(AclMemBlk,1,Key640Macipv6udfView0,rangeBitmap0,8,{155,162})
DRV_DEF_SDK_F(AclMemBlk,1,Key640Macipv6udfView0,udfIndex,3,{152,154})
DRV_DEF_SDK_F(AclMemBlk,1,Key640Macipv6udfView0,udfValid,4,{148,151})
DRV_DEF_SDK_F(AclMemBlk,1,Key640Macipv6udfView0,udf3,32,{116,147})
DRV_DEF_SDK_F(AclMemBlk,1,Key640Macipv6udfView0,udf2,32,{84,115})
DRV_DEF_SDK_F(AclMemBlk,1,Key640Macipv6udfView0,udf1,32,{52,83})
DRV_DEF_SDK_F(AclMemBlk,1,Key640Macipv6udfView0,udf0,32,{20,51})
DRV_DEF_SDK_F(AclMemBlk,1,Key640Macipv6udfView0,reserved0,20,{0,19})

DRV_DEF_M(ArlMemBlk,1) // 00380000
DRV_DEF_SDK_D(ArlMemBlk,1,ArlTable,0x0010,OP_INDIRECT,TBL_HASH,8192,3,0x00380000)
DRV_DEF_SDK_F(ArlMemBlk,1,ArlTable,portId,6,{76,81})
DRV_DEF_SDK_F(ArlMemBlk,1,ArlTable,dmacFilter,1,{75,75})
DRV_DEF_SDK_F(ArlMemBlk,1,ArlTable,smacFilter,1,{74,74})
DRV_DEF_SDK_F(ArlMemBlk,1,ArlTable,arlType,2,{72,73})
DRV_DEF_SDK_F(ArlMemBlk,1,ArlTable,stationMoved,1,{71,71})
DRV_DEF_SDK_F(ArlMemBlk,1,ArlTable,pendingLearn,1,{70,70})
DRV_DEF_SDK_F(ArlMemBlk,1,ArlTable,state,4,{66,69})
DRV_DEF_SDK_F(ArlMemBlk,1,ArlTable,mstp,6,{60,65})
DRV_DEF_SDK_F(ArlMemBlk,1,ArlTable,fid,12,{48,59})
DRV_DEF_SDK_F(ArlMemBlk,1,ArlTable,macAddr,48,{0,47})

DRV_DEF_SDK_D(ArlMemBlk,1,McTable,0x0010,OP_INDIRECT,TBL_HASH,512,3,0x00380000)
DRV_DEF_SDK_F(ArlMemBlk,1,McTable,portId,10,{76,85})
DRV_DEF_SDK_F(ArlMemBlk,1,McTable,dmacFilter,1,{75,75})
DRV_DEF_SDK_F(ArlMemBlk,1,McTable,smacFilter,1,{74,74})
DRV_DEF_SDK_F(ArlMemBlk,1,McTable,arlType,2,{72,73})
DRV_DEF_SDK_F(ArlMemBlk,1,McTable,stationMoved,1,{71,71})
DRV_DEF_SDK_F(ArlMemBlk,1,McTable,pendingLearn,1,{70,70})
DRV_DEF_SDK_F(ArlMemBlk,1,McTable,state,4,{66,69})
DRV_DEF_SDK_F(ArlMemBlk,1,McTable,mstp,6,{60,65})
DRV_DEF_SDK_F(ArlMemBlk,1,McTable,fid,12,{48,59})
DRV_DEF_SDK_F(ArlMemBlk,1,McTable,macAddr,48,{0,47})

DRV_DEF_SDK_D(ArlMemBlk,1,L2mcMappingTable,0x0008,OP_DIRECT,TBL_SRAM,512,2,0x00390000)
DRV_DEF_SDK_F(ArlMemBlk,1,L2mcMappingTable,mirrorEn,1,{42,42})
DRV_DEF_SDK_F(ArlMemBlk,1,L2mcMappingTable,egmirrorPortSel,6,{36,41})
DRV_DEF_SDK_F(ArlMemBlk,1,L2mcMappingTable,bypassEvt,1,{35,35})
DRV_DEF_SDK_F(ArlMemBlk,1,L2mcMappingTable,bypassStp,1,{34,34})
DRV_DEF_SDK_F(ArlMemBlk,1,L2mcMappingTable,dstBitmap,29,{5,33})
DRV_DEF_SDK_F(ArlMemBlk,1,L2mcMappingTable,lagBitmap,5,{0,4})

DRV_DEF_M(ArlRegBlk,1) // 00380000
DRV_DEF_SDK_D(ArlRegBlk,1,ArlCtrlReg,0x0010,OP_DIRECT,TBL_SRAM,1,3,0x00380000)
DRV_DEF_SDK_F(ArlRegBlk,1,ArlCtrlReg,daUpdateDisable,1,{94,94})
DRV_DEF_SDK_F(ArlRegBlk,1,ArlCtrlReg,moveIntThd,8,{86,93})
DRV_DEF_SDK_F(ArlRegBlk,1,ArlCtrlReg,moveIntTimer,16,{70,85})
DRV_DEF_SDK_F(ArlRegBlk,1,ArlCtrlReg,learnIntThd,8,{62,69})
DRV_DEF_SDK_F(ArlRegBlk,1,ArlCtrlReg,learnIntTimer,16,{46,61})
DRV_DEF_SDK_F(ArlRegBlk,1,ArlCtrlReg,moveFifoClr,1,{45,45})
DRV_DEF_SDK_F(ArlRegBlk,1,ArlCtrlReg,learnFifoClr,1,{44,44})
DRV_DEF_SDK_F(ArlRegBlk,1,ArlCtrlReg,ucVidSel,1,{43,43})
DRV_DEF_SDK_F(ArlRegBlk,1,ArlCtrlReg,mcVidSel,1,{42,42})
DRV_DEF_SDK_F(ArlRegBlk,1,ArlCtrlReg,sa0NotLearn,1,{41,41})
DRV_DEF_SDK_F(ArlRegBlk,1,ArlCtrlReg,sa0OrMcDrop,1,{40,40})
DRV_DEF_SDK_F(ArlRegBlk,1,ArlCtrlReg,hashSel,1,{39,39})
DRV_DEF_SDK_F(ArlRegBlk,1,ArlCtrlReg,agingEn,1,{38,38})
DRV_DEF_SDK_F(ArlRegBlk,1,ArlCtrlReg,smDirCtrl,4,{34,37})
DRV_DEF_SDK_F(ArlRegBlk,1,ArlCtrlReg,privateArlType,2,{32,33})
DRV_DEF_SDK_F(ArlRegBlk,1,ArlCtrlReg,hashSeed,32,{0,31})

DRV_DEF_SDK_D(ArlRegBlk,1,MacLkupCtrl,0x0004,OP_DIRECT,TBL_SRAM,29,1,0x00380010)
DRV_DEF_SDK_F(ArlRegBlk,1,MacLkupCtrl,bucketFullToDrop,1,{18,18})
DRV_DEF_SDK_F(ArlRegBlk,1,MacLkupCtrl,ipmcEnable,1,{17,17})
DRV_DEF_SDK_F(ArlRegBlk,1,MacLkupCtrl,smacFilter,1,{16,16})
DRV_DEF_SDK_F(ArlRegBlk,1,MacLkupCtrl,dmacFilter,1,{15,15})
DRV_DEF_SDK_F(ArlRegBlk,1,MacLkupCtrl,bucketFullToFifo,1,{14,14})
DRV_DEF_SDK_F(ArlRegBlk,1,MacLkupCtrl,newLearnPending,1,{13,13})
DRV_DEF_SDK_F(ArlRegBlk,1,MacLkupCtrl,stationMovePending,1,{12,12})
DRV_DEF_SDK_F(ArlRegBlk,1,MacLkupCtrl,learnLimitEnable,1,{11,11})
DRV_DEF_SDK_F(ArlRegBlk,1,MacLkupCtrl,learnToStatic,1,{10,10})
DRV_DEF_SDK_F(ArlRegBlk,1,MacLkupCtrl,newEnable,1,{9,9})
DRV_DEF_SDK_F(ArlRegBlk,1,MacLkupCtrl,hwMoveEnable,1,{8,8})
DRV_DEF_SDK_F(ArlRegBlk,1,MacLkupCtrl,moveLearnMode,1,{7,7})
DRV_DEF_SDK_F(ArlRegBlk,1,MacLkupCtrl,newLearnMode,1,{6,6})
DRV_DEF_SDK_F(ArlRegBlk,1,MacLkupCtrl,moveToFifo,1,{5,5})
DRV_DEF_SDK_F(ArlRegBlk,1,MacLkupCtrl,moveToDrop,1,{4,4})
DRV_DEF_SDK_F(ArlRegBlk,1,MacLkupCtrl,overlimitToFifo,1,{3,3})
DRV_DEF_SDK_F(ArlRegBlk,1,MacLkupCtrl,overlimitToDrop,1,{2,2})
DRV_DEF_SDK_F(ArlRegBlk,1,MacLkupCtrl,newsaToFifo,1,{1,1})
DRV_DEF_SDK_F(ArlRegBlk,1,MacLkupCtrl,newsaToDrop,1,{0,0})

DRV_DEF_D(ArlRegBlk,1,PortNniCfg,0x0008,OP_DIRECT,TBL_SRAM,1,2,0x00380084)
DRV_DEF_F(ArlRegBlk,1,PortNniCfg,nni,34,{0,33})

DRV_DEF_SDK_D(ArlRegBlk,1,CpuSearchCtrl,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x00380090)
DRV_DEF_SDK_F(ArlRegBlk,1,CpuSearchCtrl,searchMc,1,{20,20})
DRV_DEF_SDK_F(ArlRegBlk,1,CpuSearchCtrl,searchStart,1,{19,19})
DRV_DEF_SDK_F(ArlRegBlk,1,CpuSearchCtrl,searchType,3,{16,18})
DRV_DEF_SDK_F(ArlRegBlk,1,CpuSearchCtrl,directAddr,16,{0,15})

DRV_DEF_SDK_D(ArlRegBlk,1,CpuUpdateEntry,0x000c,OP_DIRECT,TBL_SRAM,1,3,0x00380094)
DRV_DEF_SDK_F(ArlRegBlk,1,CpuUpdateEntry,portId,10,{76,85})
DRV_DEF_SDK_F(ArlRegBlk,1,CpuUpdateEntry,dmacFilter,1,{75,75})
DRV_DEF_SDK_F(ArlRegBlk,1,CpuUpdateEntry,smacFilter,1,{74,74})
DRV_DEF_SDK_F(ArlRegBlk,1,CpuUpdateEntry,arlType,2,{72,73})
DRV_DEF_SDK_F(ArlRegBlk,1,CpuUpdateEntry,stationMoved,1,{71,71})
DRV_DEF_SDK_F(ArlRegBlk,1,CpuUpdateEntry,pendingLearn,1,{70,70})
DRV_DEF_SDK_F(ArlRegBlk,1,CpuUpdateEntry,state,4,{66,69})
DRV_DEF_SDK_F(ArlRegBlk,1,CpuUpdateEntry,mstp,6,{60,65})
DRV_DEF_SDK_F(ArlRegBlk,1,CpuUpdateEntry,fid,12,{48,59})
DRV_DEF_SDK_F(ArlRegBlk,1,CpuUpdateEntry,macAddr,48,{0,47})

DRV_DEF_SDK_D(ArlRegBlk,1,CpuSearchStatus,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x003800a8)
DRV_DEF_SDK_F(ArlRegBlk,1,CpuSearchStatus,learned,1,{2,2})
DRV_DEF_SDK_F(ArlRegBlk,1,CpuSearchStatus,hitMiss,1,{1,1})
DRV_DEF_SDK_F(ArlRegBlk,1,CpuSearchStatus,searchDone,1,{0,0})

DRV_DEF_SDK_D(ArlRegBlk,1,CpuSearchAddr,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x003800ac)
DRV_DEF_SDK_F(ArlRegBlk,1,CpuSearchAddr,tablePtr,16,{0,15})

DRV_DEF_SDK_D(ArlRegBlk,1,CpuRdbackEntry,0x000c,OP_DIRECT,TBL_SRAM,1,3,0x003800b0)
DRV_DEF_SDK_F(ArlRegBlk,1,CpuRdbackEntry,portId,10,{76,85})
DRV_DEF_SDK_F(ArlRegBlk,1,CpuRdbackEntry,dmacFilter,1,{75,75})
DRV_DEF_SDK_F(ArlRegBlk,1,CpuRdbackEntry,smacFilter,1,{74,74})
DRV_DEF_SDK_F(ArlRegBlk,1,CpuRdbackEntry,arlType,2,{72,73})
DRV_DEF_SDK_F(ArlRegBlk,1,CpuRdbackEntry,stationMoved,1,{71,71})
DRV_DEF_SDK_F(ArlRegBlk,1,CpuRdbackEntry,pendingLearn,1,{70,70})
DRV_DEF_SDK_F(ArlRegBlk,1,CpuRdbackEntry,state,4,{66,69})
DRV_DEF_SDK_F(ArlRegBlk,1,CpuRdbackEntry,mstp,6,{60,65})
DRV_DEF_SDK_F(ArlRegBlk,1,CpuRdbackEntry,fid,12,{48,59})
DRV_DEF_SDK_F(ArlRegBlk,1,CpuRdbackEntry,macAddr,48,{0,47})

DRV_DEF_SDK_D(ArlRegBlk,1,AgeTimerCtrl,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x003800d0)
DRV_DEF_SDK_F(ArlRegBlk,1,AgeTimerCtrl,agingEn,1,{30,30})
DRV_DEF_SDK_F(ArlRegBlk,1,AgeTimerCtrl,agingRTrip,20,{10,29})
DRV_DEF_SDK_F(ArlRegBlk,1,AgeTimerCtrl,agingEntry,10,{0,9})

DRV_DEF_SDK_D(ArlRegBlk,1,PortFastAgingCfg,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x003800d4)
DRV_DEF_SDK_F(ArlRegBlk,1,PortFastAgingCfg,staticEntry,1,{9,9})
DRV_DEF_SDK_F(ArlRegBlk,1,PortFastAgingCfg,glbFastAging,1,{8,8})
DRV_DEF_SDK_F(ArlRegBlk,1,PortFastAgingCfg,reserved0,1,{7,7})
DRV_DEF_SDK_F(ArlRegBlk,1,PortFastAgingCfg,portId,6,{1,6})
DRV_DEF_SDK_F(ArlRegBlk,1,PortFastAgingCfg,enable,1,{0,0})

DRV_DEF_SDK_D(ArlRegBlk,1,FidFastAgingCfg,0x0008,OP_DIRECT,TBL_SRAM,1,2,0x003800d8)
DRV_DEF_SDK_F(ArlRegBlk,1,FidFastAgingCfg,enable,1,{47,47})
DRV_DEF_SDK_F(ArlRegBlk,1,FidFastAgingCfg,portBitmap,34,{13,46})
DRV_DEF_SDK_F(ArlRegBlk,1,FidFastAgingCfg,staticEntry,1,{12,12})
DRV_DEF_SDK_F(ArlRegBlk,1,FidFastAgingCfg,fid,12,{0,11})

DRV_DEF_D(ArlRegBlk,1,MstpFastAgingCfg,0x0008,OP_DIRECT,TBL_SRAM,1,2,0x003800e0)
DRV_DEF_F(ArlRegBlk,1,MstpFastAgingCfg,enable,1,{41,41})
DRV_DEF_F(ArlRegBlk,1,MstpFastAgingCfg,portBitmap,34,{7,40})
DRV_DEF_F(ArlRegBlk,1,MstpFastAgingCfg,staticEntry,1,{6,6})
DRV_DEF_F(ArlRegBlk,1,MstpFastAgingCfg,mstp,6,{0,5})

DRV_DEF_SDK_D(ArlRegBlk,1,MacFastAgingCfg,0x000c,OP_DIRECT,TBL_SRAM,1,3,0x003800e8)
DRV_DEF_SDK_F(ArlRegBlk,1,MacFastAgingCfg,enable,1,{84,84})
DRV_DEF_SDK_F(ArlRegBlk,1,MacFastAgingCfg,ipmcFlag,1,{83,83})
DRV_DEF_SDK_F(ArlRegBlk,1,MacFastAgingCfg,portBitmap,34,{49,82})
DRV_DEF_SDK_F(ArlRegBlk,1,MacFastAgingCfg,staticEntry,1,{48,48})
DRV_DEF_SDK_F(ArlRegBlk,1,MacFastAgingCfg,mac,48,{0,47})

DRV_DEF_SDK_D(ArlRegBlk,1,FastAgingStatus,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x003800f4)
DRV_DEF_SDK_F(ArlRegBlk,1,FastAgingStatus,done,1,{0,0})

DRV_DEF_D(ArlRegBlk,1,AgingIndexReg,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x003800f8)
DRV_DEF_F(ArlRegBlk,1,AgingIndexReg,agedIndex,15,{0,14})

DRV_DEF_SDK_D(ArlRegBlk,1,SendtoFifoState,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x00380100)
DRV_DEF_SDK_F(ArlRegBlk,1,SendtoFifoState,moveFifoDeep,7,{9,15})
DRV_DEF_SDK_F(ArlRegBlk,1,SendtoFifoState,moveFifoEmpty,1,{8,8})
DRV_DEF_SDK_F(ArlRegBlk,1,SendtoFifoState,learnFifoDeep,7,{1,7})
DRV_DEF_SDK_F(ArlRegBlk,1,SendtoFifoState,learnFifoEmpty,1,{0,0})

DRV_DEF_SDK_D(ArlRegBlk,1,LearnFifoReg,0x0010,OP_DIRECT,TBL_SRAM,1,3,0x00380104)
DRV_DEF_SDK_F(ArlRegBlk,1,LearnFifoReg,isBucketFull,1,{70,70})
DRV_DEF_SDK_F(ArlRegBlk,1,LearnFifoReg,isSaOverlimit,1,{69,69})
DRV_DEF_SDK_F(ArlRegBlk,1,LearnFifoReg,learnAsPend,1,{68,68})
DRV_DEF_SDK_F(ArlRegBlk,1,LearnFifoReg,arlType,2,{66,67})
DRV_DEF_SDK_F(ArlRegBlk,1,LearnFifoReg,portId,6,{60,65})
DRV_DEF_SDK_F(ArlRegBlk,1,LearnFifoReg,fid,12,{48,59})
DRV_DEF_SDK_F(ArlRegBlk,1,LearnFifoReg,macAddr,48,{0,47})

DRV_DEF_SDK_D(ArlRegBlk,1,MoveFifoReg,0x0010,OP_DIRECT,TBL_SRAM,1,3,0x00380114)
DRV_DEF_SDK_F(ArlRegBlk,1,MoveFifoReg,isSaOverlimit,1,{76,76})
DRV_DEF_SDK_F(ArlRegBlk,1,MoveFifoReg,isMoveDone,1,{75,75})
DRV_DEF_SDK_F(ArlRegBlk,1,MoveFifoReg,learnAsMove,1,{74,74})
DRV_DEF_SDK_F(ArlRegBlk,1,MoveFifoReg,arlType,2,{72,73})
DRV_DEF_SDK_F(ArlRegBlk,1,MoveFifoReg,tablePortid,6,{66,71})
DRV_DEF_SDK_F(ArlRegBlk,1,MoveFifoReg,sourcePortid,6,{60,65})
DRV_DEF_SDK_F(ArlRegBlk,1,MoveFifoReg,fid,12,{48,59})
DRV_DEF_SDK_F(ArlRegBlk,1,MoveFifoReg,macAddr,48,{0,47})

DRV_DEF_SDK_D(ArlRegBlk,1,ArlCpuAccessReq,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x00380150)
DRV_DEF_SDK_F(ArlRegBlk,1,ArlCpuAccessReq,req,1,{31,31})
DRV_DEF_SDK_F(ArlRegBlk,1,ArlCpuAccessReq,reqType,1,{30,30})
DRV_DEF_SDK_F(ArlRegBlk,1,ArlCpuAccessReq,page,6,{24,29})
DRV_DEF_SDK_F(ArlRegBlk,1,ArlCpuAccessReq,addr,24,{0,23})

DRV_DEF_SDK_D(ArlRegBlk,1,ArlCpuAccessWdata,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x00380154)
DRV_DEF_SDK_F(ArlRegBlk,1,ArlCpuAccessWdata,data,32,{0,31})

DRV_DEF_SDK_D(ArlRegBlk,1,ArlCpuAccessRdata,0x0008,OP_DIRECT,TBL_SRAM,1,2,0x00380158)
DRV_DEF_SDK_F(ArlRegBlk,1,ArlCpuAccessRdata,complete,1,{32,32})
DRV_DEF_SDK_F(ArlRegBlk,1,ArlCpuAccessRdata,data,32,{0,31})

DRV_DEF_SDK_D(ArlRegBlk,1,PortxLearnStat,0x0004,OP_DIRECT,TBL_SRAM,34,1,0x00380200)
DRV_DEF_SDK_F(ArlRegBlk,1,PortxLearnStat,learningCounter,14,{0,13})

DRV_DEF_SDK_D(ArlRegBlk,1,PortxLearnLimit,0x0004,OP_DIRECT,TBL_SRAM,34,1,0x00380300)
DRV_DEF_SDK_F(ArlRegBlk,1,PortxLearnLimit,learningLimit,14,{0,13})

DRV_DEF_SDK_D(ArlRegBlk,1,HashCtrl,0x0008,OP_DIRECT,TBL_SRAM,4,2,0x00380400)
DRV_DEF_SDK_F(ArlRegBlk,1,HashCtrl,hashSel,2,{32,33})
DRV_DEF_SDK_F(ArlRegBlk,1,HashCtrl,seed,32,{0,31})

DRV_DEF_SDK_D(ArlRegBlk,1,McHashCtrl,0x0008,OP_DIRECT,TBL_SRAM,1,2,0x00380420)
DRV_DEF_SDK_F(ArlRegBlk,1,McHashCtrl,hashSel,2,{32,33})
DRV_DEF_SDK_F(ArlRegBlk,1,McHashCtrl,seed,32,{0,31})

DRV_DEF_D(ArlRegBlk,1,ArlDebugReg,0x0004,OP_DIRECT,TBL_SRAM,1,2,0x00380440)
DRV_DEF_F(ArlRegBlk,1,ArlDebugReg,camUsedCnt,16,{32,47})
DRV_DEF_F(ArlRegBlk,1,ArlDebugReg,daHitCnt,16,{16,31})
DRV_DEF_F(ArlRegBlk,1,ArlDebugReg,saHitCnt,16,{0,15})

DRV_DEF_M(DmaRegBlk,1)
DRV_DEF_D(DmaRegBlk,1,DmaCtrl,0x0004,OP_DIRECT,TBL_SRAM,4,1,0x00028000)
DRV_DEF_F(DmaRegBlk,1,DmaCtrl,rs,1,{0,0})

DRV_DEF_D(DmaRegBlk,1,DmaStatus,0x0004,OP_DIRECT,TBL_SRAM,4,1,0x00028010)
DRV_DEF_F(DmaRegBlk,1,DmaStatus,curSta,3,{28,30})
DRV_DEF_F(DmaRegBlk,1,DmaStatus,compCnt,8,{20,27})
DRV_DEF_F(DmaRegBlk,1,DmaStatus,compErrCnt,4,{16,19})
DRV_DEF_F(DmaRegBlk,1,DmaStatus,busErrCnt,4,{12,15})
DRV_DEF_F(DmaRegBlk,1,DmaStatus,timeoutCnt,4,{8,11})
DRV_DEF_F(DmaRegBlk,1,DmaStatus,haltedCnt,4,{4,7})
DRV_DEF_F(DmaRegBlk,1,DmaStatus,reserve,1,{3,3})
DRV_DEF_F(DmaRegBlk,1,DmaStatus,empty,1,{2,2})
DRV_DEF_F(DmaRegBlk,1,DmaStatus,idle,1,{1,1})
DRV_DEF_F(DmaRegBlk,1,DmaStatus,halted,1,{0,0})

DRV_DEF_D(DmaRegBlk,1,DmaDescrptr,0x0004,OP_DIRECT,TBL_SRAM,4,1,0x00028020)
DRV_DEF_F(DmaRegBlk,1,DmaDescrptr,headPtr,32,{0,31})

DRV_DEF_D(DmaRegBlk,1,DmaChainCtrl,0x0004,OP_DIRECT,TBL_SRAM,4,1,0x00028050)
DRV_DEF_F(DmaRegBlk,1,DmaChainCtrl,compMode,1,{16,16})
DRV_DEF_F(DmaRegBlk,1,DmaChainCtrl,compWaitTimer,16,{0,15})

DRV_DEF_D(DmaRegBlk,1,DmaGlbCtrl,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x00028060)
DRV_DEF_F(DmaRegBlk,1,DmaGlbCtrl,ahbTimeoutEn,1,{4,4})
DRV_DEF_F(DmaRegBlk,1,DmaGlbCtrl,tranByteType,1,{3,3})
DRV_DEF_F(DmaRegBlk,1,DmaGlbCtrl,burstSize,3,{0,2})

DRV_DEF_D(DmaRegBlk,1,DmaInt,0x0004,OP_DIRECT,TBL_SRAM,4,1,0x00028030)
DRV_DEF_F(DmaRegBlk,1,DmaInt,irqDelay,8,{11,18})
DRV_DEF_F(DmaRegBlk,1,DmaInt,irqThd,8,{3,10})
DRV_DEF_F(DmaRegBlk,1,DmaInt,errIrqen,1,{2,2})
DRV_DEF_F(DmaRegBlk,1,DmaInt,dlyIrqen,1,{1,1})
DRV_DEF_F(DmaRegBlk,1,DmaInt,iocIrqen,1,{0,0})

DRV_DEF_D(DmaRegBlk,1,DmaQueue,0x0008,OP_DIRECT,TBL_SRAM,1,2,0x00028040)
DRV_DEF_F(DmaRegBlk,1,DmaQueue,dmaId,48,{0,47})

DRV_DEF_D(DmaRegBlk,1,DmaDcbStatus,0x0010,OP_DIRECT,TBL_SRAM,4,3,0x00028080)
DRV_DEF_F(DmaRegBlk,1,DmaDcbStatus,compt,1,{95,95})
DRV_DEF_F(DmaRegBlk,1,DmaDcbStatus,decerr,1,{94,94})
DRV_DEF_F(DmaRegBlk,1,DmaDcbStatus,slverr,1,{93,93})
DRV_DEF_F(DmaRegBlk,1,DmaDcbStatus,comperr,1,{92,92})
DRV_DEF_F(DmaRegBlk,1,DmaDcbStatus,eof,1,{91,91})
DRV_DEF_F(DmaRegBlk,1,DmaDcbStatus,sof,1,{90,90})
DRV_DEF_F(DmaRegBlk,1,DmaDcbStatus,chain,1,{89,89})
DRV_DEF_F(DmaRegBlk,1,DmaDcbStatus,reserve,9,{80,88})
DRV_DEF_F(DmaRegBlk,1,DmaDcbStatus,length,16,{64,79})
DRV_DEF_F(DmaRegBlk,1,DmaDcbStatus,bufPtr,32,{32,63})
DRV_DEF_F(DmaRegBlk,1,DmaDcbStatus,nxtDescrPtr,32,{0,31})

DRV_DEF_D(DmaRegBlk,1,DmaDebugInfo,0x0010,OP_DIRECT,TBL_SRAM,1,2,0x000280c0)
DRV_DEF_F(DmaRegBlk,1,DmaDebugInfo,txCurDmaId,1,{53,53})
DRV_DEF_F(DmaRegBlk,1,DmaDebugInfo,rxCurDmaId,1,{52,52})
DRV_DEF_F(DmaRegBlk,1,DmaDebugInfo,txBufBurstDatReady,1,{51,51})
DRV_DEF_F(DmaRegBlk,1,DmaDebugInfo,rxBufBurstDatReady,1,{50,50})
DRV_DEF_F(DmaRegBlk,1,DmaDebugInfo,tranPid,1,{49,49})
DRV_DEF_F(DmaRegBlk,1,DmaDebugInfo,tranDir,1,{48,48})
DRV_DEF_F(DmaRegBlk,1,DmaDebugInfo,tranReq,1,{47,47})
DRV_DEF_F(DmaRegBlk,1,DmaDebugInfo,tranReqInfo,47,{0,46})

DRV_DEF_D(DmaRegBlk,1,DmaAhbCnt,0x0004,OP_DIRECT,TBL_SRAM,4,1,0x000280e0)
DRV_DEF_F(DmaRegBlk,1,DmaAhbCnt,cnt,8,{0,7})

DRV_DEF_D(DmaRegBlk,1,DmaDescriptor,0x0008,OP_DIRECT,TBL_SRAM,1,3,0x00028000)
DRV_DEF_F(DmaRegBlk,1,DmaDescriptor,compt,1,{95,95})
DRV_DEF_F(DmaRegBlk,1,DmaDescriptor,decerr,1,{94,94})
DRV_DEF_F(DmaRegBlk,1,DmaDescriptor,slverr,1,{93,93})
DRV_DEF_F(DmaRegBlk,1,DmaDescriptor,comperr,1,{92,92})
DRV_DEF_F(DmaRegBlk,1,DmaDescriptor,eof,1,{91,91})
DRV_DEF_F(DmaRegBlk,1,DmaDescriptor,sof,1,{90,90})
DRV_DEF_F(DmaRegBlk,1,DmaDescriptor,chain,1,{89,89})
DRV_DEF_F(DmaRegBlk,1,DmaDescriptor,reserve,9,{80,88})
DRV_DEF_F(DmaRegBlk,1,DmaDescriptor,length,16,{64,79})
DRV_DEF_F(DmaRegBlk,1,DmaDescriptor,bufPtr,32,{32,63})
DRV_DEF_F(DmaRegBlk,1,DmaDescriptor,nxtDescrPtr,32,{0,31})

DRV_DEF_M(GlobalRegBlk,1)
DRV_DEF_SDK_D(GlobalRegBlk,1,Version,0x0010,OP_DIRECT,TBL_SRAM,1,1,0x00000000)
DRV_DEF_SDK_F(GlobalRegBlk,1,Version,version,32,{0,31})

DRV_DEF_SDK_D(GlobalRegBlk,1,GlobalIntEn,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x00000600)
DRV_DEF_SDK_F(GlobalRegBlk,1,GlobalIntEn,gblInt,1,{0,0})

DRV_DEF_SDK_D(GlobalRegBlk,1,GlobalIntMaskSet,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x00000610)
DRV_DEF_SDK_F(GlobalRegBlk,1,GlobalIntMaskSet,dmaErrInt,4,{10,13})
DRV_DEF_SDK_F(GlobalRegBlk,1,GlobalIntMaskSet,dmaCompInt,4,{6,9})
DRV_DEF_SDK_F(GlobalRegBlk,1,GlobalIntMaskSet,fifoErrInt,1,{5,5})
DRV_DEF_SDK_F(GlobalRegBlk,1,GlobalIntMaskSet,halfDuplexInt,1,{4,4})
DRV_DEF_SDK_F(GlobalRegBlk,1,GlobalIntMaskSet,eccErrInt,1,{3,3})
DRV_DEF_SDK_F(GlobalRegBlk,1,GlobalIntMaskSet,moveFifoInt,1,{2,2})
DRV_DEF_SDK_F(GlobalRegBlk,1,GlobalIntMaskSet,learnFifoInt,1,{1,1})
DRV_DEF_SDK_F(GlobalRegBlk,1,GlobalIntMaskSet,gblInt,1,{0,0})

DRV_DEF_SDK_D(GlobalRegBlk,1,GlobalIntMaskReset,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x00000660)
DRV_DEF_SDK_F(GlobalRegBlk,1,GlobalIntMaskReset,dmaErrInt,4,{10,13})
DRV_DEF_SDK_F(GlobalRegBlk,1,GlobalIntMaskReset,dmaCompInt,4,{6,9})
DRV_DEF_SDK_F(GlobalRegBlk,1,GlobalIntMaskReset,fifoErrInt,1,{5,5})
DRV_DEF_SDK_F(GlobalRegBlk,1,GlobalIntMaskReset,halfDuplexInt,1,{4,4})
DRV_DEF_SDK_F(GlobalRegBlk,1,GlobalIntMaskReset,eccErrInt,1,{3,3})
DRV_DEF_SDK_F(GlobalRegBlk,1,GlobalIntMaskReset,moveFifoInt,1,{2,2})
DRV_DEF_SDK_F(GlobalRegBlk,1,GlobalIntMaskReset,learnFifoInt,1,{1,1})
DRV_DEF_SDK_F(GlobalRegBlk,1,GlobalIntMaskReset,gblInt,1,{0,0})

DRV_DEF_SDK_D(GlobalRegBlk,1,GlobalIntStatusSet,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x00000620)
DRV_DEF_SDK_F(GlobalRegBlk,1,GlobalIntStatusSet,dmaErrInt,4,{10,13})
DRV_DEF_SDK_F(GlobalRegBlk,1,GlobalIntStatusSet,dmaCompInt,4,{6,9})
DRV_DEF_SDK_F(GlobalRegBlk,1,GlobalIntStatusSet,fifoErrInt,1,{5,5})
DRV_DEF_SDK_F(GlobalRegBlk,1,GlobalIntStatusSet,halfDuplexInt,1,{4,4})
DRV_DEF_SDK_F(GlobalRegBlk,1,GlobalIntStatusSet,eccErrInt,1,{3,3})
DRV_DEF_SDK_F(GlobalRegBlk,1,GlobalIntStatusSet,moveFifoInt,1,{2,2})
DRV_DEF_SDK_F(GlobalRegBlk,1,GlobalIntStatusSet,learnFifoInt,1,{1,1})
DRV_DEF_SDK_F(GlobalRegBlk,1,GlobalIntStatusSet,gblInt,1,{0,0})

DRV_DEF_SDK_D(GlobalRegBlk,1,GlobalIntStatusReset,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x00000670)
DRV_DEF_SDK_F(GlobalRegBlk,1,GlobalIntStatusReset,dmaErrInt,4,{10,13})
DRV_DEF_SDK_F(GlobalRegBlk,1,GlobalIntStatusReset,dmaCompInt,4,{6,9})
DRV_DEF_SDK_F(GlobalRegBlk,1,GlobalIntStatusReset,fifoErrInt,1,{5,5})
DRV_DEF_SDK_F(GlobalRegBlk,1,GlobalIntStatusReset,halfDuplexInt,1,{4,4})
DRV_DEF_SDK_F(GlobalRegBlk,1,GlobalIntStatusReset,eccErrInt,1,{3,3})
DRV_DEF_SDK_F(GlobalRegBlk,1,GlobalIntStatusReset,moveFifoInt,1,{2,2})
DRV_DEF_SDK_F(GlobalRegBlk,1,GlobalIntStatusReset,learnFifoInt,1,{1,1})
DRV_DEF_SDK_F(GlobalRegBlk,1,GlobalIntStatusReset,gblInt,1,{0,0})

DRV_DEF_D(GlobalRegBlk,1,IntPluseWidth,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x00000700)
DRV_DEF_F(GlobalRegBlk,1,IntPluseWidth,cnt,32,{0,31})

DRV_DEF_D(GlobalRegBlk,1,IntPortMode,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x00000704)
DRV_DEF_F(GlobalRegBlk,1,IntPortMode,mode,1,{0,0})

DRV_DEF_M(IntfRegBlk,1)
DRV_DEF_D(IntfRegBlk,1,RgmiiClkPhaseCtl,0x0004,OP_DIRECT,TBL_SRAM,2,1,0x000201e0)
DRV_DEF_F(IntfRegBlk,1,RgmiiClkPhaseCtl,rxAdjust,4,{5,8})
DRV_DEF_F(IntfRegBlk,1,RgmiiClkPhaseCtl,txMode,1,{4,4})
DRV_DEF_F(IntfRegBlk,1,RgmiiClkPhaseCtl,txAdjust,4,{0,3})

DRV_DEF_SDK_D(IntfRegBlk,1,MacRxCtrl,0x0004,OP_DIRECT,TBL_SRAM,29,1,0x00020200)
DRV_DEF_SDK_F(IntfRegBlk,1,MacRxCtrl,swapMac,1,{10,10})
DRV_DEF_SDK_F(IntfRegBlk,1,MacRxCtrl,tagAwareEn,1,{9,9})
DRV_DEF_SDK_F(IntfRegBlk,1,MacRxCtrl,minFrameLen,2,{7,8})
DRV_DEF_SDK_F(IntfRegBlk,1,MacRxCtrl,reserved0,1,{6,6})
DRV_DEF_SDK_F(IntfRegBlk,1,MacRxCtrl,flowControlEn,1,{5,5})
DRV_DEF_SDK_F(IntfRegBlk,1,MacRxCtrl,crcStripEn,1,{4,4})
DRV_DEF_SDK_F(IntfRegBlk,1,MacRxCtrl,crcCheckEn,1,{3,3})
DRV_DEF_SDK_F(IntfRegBlk,1,MacRxCtrl,preCheckEn,1,{2,2})
DRV_DEF_SDK_F(IntfRegBlk,1,MacRxCtrl,loopbackEn,1,{1,1})
DRV_DEF_SDK_F(IntfRegBlk,1,MacRxCtrl,portEn,1,{0,0})

DRV_DEF_SDK_D(IntfRegBlk,1,MacTxCtrl,0x0004,OP_DIRECT,TBL_SRAM,29,1,0x00020280)
DRV_DEF_SDK_F(IntfRegBlk,1,MacTxCtrl,eeeEn,1,{19,19})
DRV_DEF_SDK_F(IntfRegBlk,1,MacTxCtrl,eeeWakeupTimeSel,2,{17,18})
DRV_DEF_SDK_F(IntfRegBlk,1,MacTxCtrl,pauseTrig,1,{16,16})
DRV_DEF_SDK_F(IntfRegBlk,1,MacTxCtrl,pauseOnOff,1,{15,15})
DRV_DEF_SDK_F(IntfRegBlk,1,MacTxCtrl,flowControlEn,1,{14,14})
DRV_DEF_SDK_F(IntfRegBlk,1,MacTxCtrl,crcInvertEn,1,{13,13})
DRV_DEF_SDK_F(IntfRegBlk,1,MacTxCtrl,crcInsertEn,1,{12,12})
DRV_DEF_SDK_F(IntfRegBlk,1,MacTxCtrl,preSel,1,{11,11})
DRV_DEF_SDK_F(IntfRegBlk,1,MacTxCtrl,ipgSel,3,{8,10})
DRV_DEF_SDK_F(IntfRegBlk,1,MacTxCtrl,speedSel,2,{6,7})
DRV_DEF_SDK_F(IntfRegBlk,1,MacTxCtrl,intfType,3,{3,5})
DRV_DEF_SDK_F(IntfRegBlk,1,MacTxCtrl,duplexMode,1,{2,2})
DRV_DEF_SDK_F(IntfRegBlk,1,MacTxCtrl,loopbackEn,1,{1,1})
DRV_DEF_SDK_F(IntfRegBlk,1,MacTxCtrl,portEn,1,{0,0})

DRV_DEF_D(IntfRegBlk,1,PauseTimeCtrl,0x0004,OP_DIRECT,TBL_SRAM,29,1,0x00020300)
DRV_DEF_F(IntfRegBlk,1,PauseTimeCtrl,value,16,{0,15})

DRV_DEF_D(IntfRegBlk,1,PauseIntervalCtrl,0x0004,OP_DIRECT,TBL_SRAM,29,1,0x00020380)
DRV_DEF_F(IntfRegBlk,1,PauseIntervalCtrl,value,4,{0,3})

DRV_DEF_SDK_D(IntfRegBlk,1,MaxFrameLen,0x0004,OP_DIRECT,TBL_SRAM,29,1,0x00020400)
DRV_DEF_SDK_F(IntfRegBlk,1,MaxFrameLen,len,14,{0,13})

DRV_DEF_SDK_D(IntfRegBlk,1,JumboFrameLen,0x0004,OP_DIRECT,TBL_SRAM,29,1,0x00020480)
DRV_DEF_SDK_F(IntfRegBlk,1,JumboFrameLen,len,14,{0,13})

DRV_DEF_D(IntfRegBlk,1,PesudoRandomSeed,0x0004,OP_DIRECT,TBL_SRAM,29,1,0x00020500)
DRV_DEF_F(IntfRegBlk,1,PesudoRandomSeed,seed,16,{0,15})

DRV_DEF_D(IntfRegBlk,1,JamPattern,0x0004,OP_DIRECT,TBL_SRAM,29,1,0x00020580)
DRV_DEF_F(IntfRegBlk,1,JamPattern,pattern,32,{0,31})

DRV_DEF_D(IntfRegBlk,1,MacStatus,0x0008,OP_DIRECT,TBL_SRAM,1,2,0x00020600)
DRV_DEF_F(IntfRegBlk,1,MacStatus,lateColErr,29,{32,60})
DRV_DEF_F(IntfRegBlk,1,MacStatus,reserve,3,{29,31})
DRV_DEF_F(IntfRegBlk,1,MacStatus,excColErr,29,{0,28})

DRV_DEF_SDK_D(IntfRegBlk,1,CpuMacCtrl,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x00020680)
DRV_DEF_SDK_F(IntfRegBlk,1,CpuMacCtrl,noPtagDrop,2,{3,4})
DRV_DEF_SDK_F(IntfRegBlk,1,CpuMacCtrl,cpuEn,2,{1,2})
DRV_DEF_SDK_F(IntfRegBlk,1,CpuMacCtrl,mode,1,{0,0})

DRV_DEF_D(IntfRegBlk,1,EeeSleepTime,0x0004,OP_DIRECT,TBL_SRAM,29,1,0x00020700)
DRV_DEF_F(IntfRegBlk,1,EeeSleepTime,timer,25,{0,24})

DRV_DEF_D(IntfRegBlk,1,EeeWakeupTime,0x0004,OP_DIRECT,TBL_SRAM,4,1,0x00020780)
DRV_DEF_F(IntfRegBlk,1,EeeWakeupTime,timer,16,{0,15})

DRV_DEF_D(IntfRegBlk,1,DebugState,0x0004,OP_DIRECT,TBL_SRAM,16,1,0x00020b00)
DRV_DEF_F(IntfRegBlk,1,DebugState,state,32,{0,31})

DRV_DEF_D(IntfRegBlk,1,MacCntCtrl,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x00020b80)
DRV_DEF_F(IntfRegBlk,1,MacCntCtrl,clr,1,{0,0})

DRV_DEF_D(IntfRegBlk,1,MacCnt,0x0010,OP_DIRECT,TBL_SRAM,33,4,0x00020c00)
DRV_DEF_F(IntfRegBlk,1,MacCnt,cnt,48,{80,127})
DRV_DEF_F(IntfRegBlk,1,MacCnt,gmiiRaise,16,{64,79})
DRV_DEF_F(IntfRegBlk,1,MacCnt,geEop,16,{48,63})
DRV_DEF_F(IntfRegBlk,1,MacCnt,geSop,16,{32,47})
DRV_DEF_F(IntfRegBlk,1,MacCnt,xgEop,16,{16,31})
DRV_DEF_F(IntfRegBlk,1,MacCnt,xgSop,16,{0,15})

DRV_DEF_M(MibMemBlk,1)
DRV_DEF_SDK_D(MibMemBlk,1,MibRx,0x0100,OP_DIRECT,TBL_SRAM,29,24,0x00034000)
DRV_DEF_SDK_F(MibMemBlk,1,MibRx,rxgoodjumbos,32,{736,767})
DRV_DEF_SDK_F(MibMemBlk,1,MibRx,rxjumbopkt,32,{704,735})
DRV_DEF_SDK_F(MibMemBlk,1,MibRx,rxpkts1024tomaxpktoctets,32,{672,703})
DRV_DEF_SDK_F(MibMemBlk,1,MibRx,rxpkts512to1023octets,32,{640,671})
DRV_DEF_SDK_F(MibMemBlk,1,MibRx,rxpkts256to511octets,32,{608,639})
DRV_DEF_SDK_F(MibMemBlk,1,MibRx,rxpkts128to255octets,32,{576,607})
DRV_DEF_SDK_F(MibMemBlk,1,MibRx,rxpkts65to127octets,32,{544,575})
DRV_DEF_SDK_F(MibMemBlk,1,MibRx,rxpkts64octets,32,{512,543})
DRV_DEF_SDK_F(MibMemBlk,1,MibRx,rxpkts60to63octets,32,{480,511})
DRV_DEF_SDK_F(MibMemBlk,1,MibRx,rxoutofrangeerrors,32,{448,479})
DRV_DEF_SDK_F(MibMemBlk,1,MibRx,inrangeerrors,32,{416,447})
DRV_DEF_SDK_F(MibMemBlk,1,MibRx,rxpausepkts,32,{384,415})
DRV_DEF_SDK_F(MibMemBlk,1,MibRx,rxfcserrors,32,{352,383})
DRV_DEF_SDK_F(MibMemBlk,1,MibRx,rxalignmenterrors,32,{320,351})
DRV_DEF_SDK_F(MibMemBlk,1,MibRx,rxjabbers,32,{288,319})
DRV_DEF_SDK_F(MibMemBlk,1,MibRx,rxfragments,32,{256,287})
DRV_DEF_SDK_F(MibMemBlk,1,MibRx,rxoversizepkts,32,{224,255})
DRV_DEF_SDK_F(MibMemBlk,1,MibRx,rxundersizepkts,32,{192,223})
DRV_DEF_SDK_F(MibMemBlk,1,MibRx,rxunicastpkts,32,{160,191})
DRV_DEF_SDK_F(MibMemBlk,1,MibRx,rxmulticastpkts,32,{128,159})
DRV_DEF_SDK_F(MibMemBlk,1,MibRx,rxbroadcastpkts,32,{96,127})
DRV_DEF_SDK_F(MibMemBlk,1,MibRx,rxgoodoctets,32,{64,95})
DRV_DEF_SDK_F(MibMemBlk,1,MibRx,rxoctets,64,{0,63})

DRV_DEF_SDK_D(MibMemBlk,1,MibTx,0x0100,OP_DIRECT,TBL_SRAM,29,15,0x00034060)
DRV_DEF_SDK_F(MibMemBlk,1,MibTx,txmorethanjumbopkt,32,{448,479})
DRV_DEF_SDK_F(MibMemBlk,1,MibTx,txjumbopkt,32,{416,447})
DRV_DEF_SDK_F(MibMemBlk,1,MibTx,txpkts1024tomaxpktoctets,32,{384,415})
DRV_DEF_SDK_F(MibMemBlk,1,MibTx,txpkts512to1023octets,32,{352,383})
DRV_DEF_SDK_F(MibMemBlk,1,MibTx,txpkts256to511octets,32,{320,351})
DRV_DEF_SDK_F(MibMemBlk,1,MibTx,txpkts128to255octets,32,{288,319})
DRV_DEF_SDK_F(MibMemBlk,1,MibTx,txpkts65to127octets,32,{256,287})
DRV_DEF_SDK_F(MibMemBlk,1,MibTx,txpkts64octets,32,{224,255})
DRV_DEF_SDK_F(MibMemBlk,1,MibTx,txpkts60to63octets,32,{192,223})
DRV_DEF_SDK_F(MibMemBlk,1,MibTx,txpausepkts,32,{160,191})
DRV_DEF_SDK_F(MibMemBlk,1,MibTx,txunicastpkts,32,{128,159})
DRV_DEF_SDK_F(MibMemBlk,1,MibTx,txmulticastpkts,32,{96,127})
DRV_DEF_SDK_F(MibMemBlk,1,MibTx,txbroadcastpkts,32,{64,95})
DRV_DEF_SDK_F(MibMemBlk,1,MibTx,txoctets,64,{0,63})

DRV_DEF_M(MibRegBlk,1)
DRV_DEF_SDK_D(MibRegBlk,1,MibCfg,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x00030000)
DRV_DEF_SDK_F(MibRegBlk,1,MibCfg,mibCmdChn,5,{4,8})
DRV_DEF_SDK_F(MibRegBlk,1,MibCfg,mibCmdDir,1,{3,3})
DRV_DEF_SDK_F(MibRegBlk,1,MibCfg,snapMode,1,{2,2})
DRV_DEF_SDK_F(MibRegBlk,1,MibCfg,mibCmd,1,{1,1})
DRV_DEF_SDK_F(MibRegBlk,1,MibCfg,mibCmdEn,1,{0,0})

DRV_DEF_M(MmuMemBlk,1)
DRV_DEF_SDK_D(MmuMemBlk,1,IngMmuPortCnt,0x0004,OP_INDIRECT,TBL_SRAM,29,1,0x00080200)
DRV_DEF_SDK_F(MmuMemBlk,1,IngMmuPortCnt,pktCnt,10,{12,21})
DRV_DEF_SDK_F(MmuMemBlk,1,IngMmuPortCnt,cellCnt,12,{0,11})

DRV_DEF_SDK_D(MmuMemBlk,1,IngMmuPortCtrl,0x0010,OP_INDIRECT,TBL_SRAM,29,3,0x00080400)
DRV_DEF_SDK_F(MmuMemBlk,1,IngMmuPortCtrl,cellHead,9,{61,69})
DRV_DEF_SDK_F(MmuMemBlk,1,IngMmuPortCtrl,cellOffset,9,{52,60})
DRV_DEF_SDK_F(MmuMemBlk,1,IngMmuPortCtrl,cellShare,9,{43,51})
DRV_DEF_SDK_F(MmuMemBlk,1,IngMmuPortCtrl,cellDynamic,1,{42,42})
DRV_DEF_SDK_F(MmuMemBlk,1,IngMmuPortCtrl,cellMin,9,{33,41})
DRV_DEF_SDK_F(MmuMemBlk,1,IngMmuPortCtrl,pktHead,8,{25,32})
DRV_DEF_SDK_F(MmuMemBlk,1,IngMmuPortCtrl,pktOffset,8,{17,24})
DRV_DEF_SDK_F(MmuMemBlk,1,IngMmuPortCtrl,pktShare,8,{9,16})
DRV_DEF_SDK_F(MmuMemBlk,1,IngMmuPortCtrl,pktDynamic,1,{8,8})
DRV_DEF_SDK_F(MmuMemBlk,1,IngMmuPortCtrl,pktMin,8,{0,7})

DRV_DEF_D(MmuMemBlk,1,IngressMibTable,0x0004,OP_DIRECT,TBL_SRAM,640,1,0x00090000)
DRV_DEF_F(MmuMemBlk,1,IngressMibTable,cnt,32,{0,31})

DRV_DEF_SDK_D(MmuMemBlk,1,QueueMinMax,0x0010,OP_INDIRECT,TBL_SRAM,272,3,0x00084000)
DRV_DEF_SDK_F(MmuMemBlk,1,QueueMinMax,bucketGrain,3,{65,67})
DRV_DEF_SDK_F(MmuMemBlk,1,QueueMinMax,meterMode,1,{64,64})
DRV_DEF_SDK_F(MmuMemBlk,1,QueueMinMax,maxRefreshCnt,19,{45,63})
DRV_DEF_SDK_F(MmuMemBlk,1,QueueMinMax,maxThreshold,12,{33,44})
DRV_DEF_SDK_F(MmuMemBlk,1,QueueMinMax,minRefreshCnt,19,{14,32})
DRV_DEF_SDK_F(MmuMemBlk,1,QueueMinMax,minThreshold,12,{2,13})
DRV_DEF_SDK_F(MmuMemBlk,1,QueueMinMax,maxMeterEn,1,{1,1})
DRV_DEF_SDK_F(MmuMemBlk,1,QueueMinMax,minMeterEn,1,{0,0})

DRV_DEF_SDK_D(MmuMemBlk,1,QueueWeight,0x0004,OP_INDIRECT,TBL_SRAM,272,1,0x00086000)
DRV_DEF_SDK_F(MmuMemBlk,1,QueueWeight,weight,7,{0,6})

DRV_DEF_M(MmuRegBlk,1)
DRV_DEF_SDK_D(MmuRegBlk,1,MmuCpuAccessReq,0x0010,OP_DIRECT,TBL_SRAM,1,1,0x00080800)
DRV_DEF_SDK_F(MmuRegBlk,1,MmuCpuAccessReq,req,1,{31,31})
DRV_DEF_SDK_F(MmuRegBlk,1,MmuCpuAccessReq,reqType,1,{30,30})
DRV_DEF_SDK_F(MmuRegBlk,1,MmuCpuAccessReq,page,6,{24,29})
DRV_DEF_SDK_F(MmuRegBlk,1,MmuCpuAccessReq,addr,24,{0,23})

DRV_DEF_SDK_D(MmuRegBlk,1,MmuCpuAccessWdata,0x0020,OP_DIRECT,TBL_SRAM,1,8,0x00080840)
DRV_DEF_SDK_F(MmuRegBlk,1,MmuCpuAccessWdata,data,256,{0,255})

DRV_DEF_SDK_D(MmuRegBlk,1,MmuCpuAccessRdata,0x0040,OP_DIRECT,TBL_SRAM,1,9,0x00080880)
DRV_DEF_SDK_F(MmuRegBlk,1,MmuCpuAccessRdata,complete,1,{256,256})
DRV_DEF_SDK_F(MmuRegBlk,1,MmuCpuAccessRdata,data,256,{0,255})

DRV_DEF_D(MmuRegBlk,1,IngMmuPortEn,0x0008,OP_DIRECT,TBL_SRAM,1,1,0x00080000)
DRV_DEF_F(MmuRegBlk,1,IngMmuPortEn,clrAllDebug,1,{29,29})
DRV_DEF_F(MmuRegBlk,1,IngMmuPortEn,enable,29,{0,28})

DRV_DEF_SDK_D(MmuRegBlk,1,IngMmuXoffEn,0x0008,OP_DIRECT,TBL_SRAM,1,1,0x00080008)
DRV_DEF_SDK_F(MmuRegBlk,1,IngMmuXoffEn,enable,29,{0,28})

DRV_DEF_SDK_D(MmuRegBlk,1,IngMmuGlbCnt,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x00080010)
DRV_DEF_SDK_F(MmuRegBlk,1,IngMmuGlbCnt,pktCnt,10,{12,21})
DRV_DEF_SDK_F(MmuRegBlk,1,IngMmuGlbCnt,cellCnt,12,{0,11})

DRV_DEF_D(MmuRegBlk,1,IngMmuGlbCntMax,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x00080014)
DRV_DEF_F(MmuRegBlk,1,IngMmuGlbCntMax,pktCnt,10,{12,21})
DRV_DEF_F(MmuRegBlk,1,IngMmuGlbCntMax,cellCnt,12,{0,11})

DRV_DEF_D(MmuRegBlk,1,IngMmuGlbState,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x00080020)
DRV_DEF_F(MmuRegBlk,1,IngMmuGlbState,pktState,2,{24,25})
DRV_DEF_F(MmuRegBlk,1,IngMmuGlbState,cellState,2,{22,23})
DRV_DEF_F(MmuRegBlk,1,IngMmuGlbState,totalCellShare,12,{10,21})
DRV_DEF_F(MmuRegBlk,1,IngMmuGlbState,totalPktShare,10,{0,9})

DRV_DEF_SDK_D(MmuRegBlk,1,IngMmuGlbCtrl,0x0010,OP_DIRECT,TBL_SRAM,1,3,0x00080030)
DRV_DEF_SDK_F(MmuRegBlk,1,IngMmuGlbCtrl,thdDropEn,1,{68,68})
DRV_DEF_SDK_F(MmuRegBlk,1,IngMmuGlbCtrl,pktDrop,8,{60,67})
DRV_DEF_SDK_F(MmuRegBlk,1,IngMmuGlbCtrl,pktPause,8,{52,59})
DRV_DEF_SDK_F(MmuRegBlk,1,IngMmuGlbCtrl,pktOffset,8,{44,51})
DRV_DEF_SDK_F(MmuRegBlk,1,IngMmuGlbCtrl,pktShare,8,{36,43})
DRV_DEF_SDK_F(MmuRegBlk,1,IngMmuGlbCtrl,cellDrop,9,{27,35})
DRV_DEF_SDK_F(MmuRegBlk,1,IngMmuGlbCtrl,cellPause,9,{18,26})
DRV_DEF_SDK_F(MmuRegBlk,1,IngMmuGlbCtrl,cellOffset,9,{9,17})
DRV_DEF_SDK_F(MmuRegBlk,1,IngMmuGlbCtrl,cellShare,9,{0,8})

DRV_DEF_SDK_D(MmuRegBlk,1,IngMmuPortState,0x0004,OP_DIRECT,TBL_SRAM,29,1,0x00080300)
DRV_DEF_SDK_F(MmuRegBlk,1,IngMmuPortState,pktState,2,{2,3})
DRV_DEF_SDK_F(MmuRegBlk,1,IngMmuPortState,cellState,2,{0,1})

DRV_DEF_SDK_D(MmuRegBlk,1,MmuCellPoolDebug,0x0010,OP_DIRECT,TBL_SRAM,1,2,0x00080040)
DRV_DEF_SDK_F(MmuRegBlk,1,MmuCellPoolDebug,poolDeep,15,{48,62})
DRV_DEF_SDK_F(MmuRegBlk,1,MmuCellPoolDebug,poolFull,1,{47,47})
DRV_DEF_SDK_F(MmuRegBlk,1,MmuCellPoolDebug,poolEmpty,1,{46,46})
DRV_DEF_SDK_F(MmuRegBlk,1,MmuCellPoolDebug,poolTailErr,8,{38,45})
DRV_DEF_SDK_F(MmuRegBlk,1,MmuCellPoolDebug,poolFullErr,8,{30,37})
DRV_DEF_SDK_F(MmuRegBlk,1,MmuCellPoolDebug,poolEmptyDrop,16,{14,29})
DRV_DEF_SDK_F(MmuRegBlk,1,MmuCellPoolDebug,recycleFifoFullErr,8,{6,13})
DRV_DEF_SDK_F(MmuRegBlk,1,MmuCellPoolDebug,assignFifoDeep,6,{0,5})

DRV_DEF_D(MmuRegBlk,1,MmuPktPoolDebug,0x0010,OP_DIRECT,TBL_SRAM,1,2,0x00080050)
DRV_DEF_F(MmuRegBlk,1,MmuPktPoolDebug,poolDeep,14,{48,61})
DRV_DEF_F(MmuRegBlk,1,MmuPktPoolDebug,poolFull,1,{47,47})
DRV_DEF_F(MmuRegBlk,1,MmuPktPoolDebug,poolEmpty,1,{46,46})
DRV_DEF_F(MmuRegBlk,1,MmuPktPoolDebug,poolTailErr,8,{38,45})
DRV_DEF_F(MmuRegBlk,1,MmuPktPoolDebug,poolFullErr,8,{30,37})
DRV_DEF_F(MmuRegBlk,1,MmuPktPoolDebug,poolEmptyDrop,16,{14,29})
DRV_DEF_F(MmuRegBlk,1,MmuPktPoolDebug,recycleFifoFullErr,8,{6,13})
DRV_DEF_F(MmuRegBlk,1,MmuPktPoolDebug,assignFifoDeep,6,{0,5})

DRV_DEF_D(MmuRegBlk,1,MmuIngCntDebug,0x0020,OP_DIRECT,TBL_SRAM,1,7,0x00080060)
DRV_DEF_F(MmuRegBlk,1,MmuIngCntDebug,debugDrop,16,{187,202})
DRV_DEF_F(MmuRegBlk,1,MmuIngCntDebug,rrfifoFullErr,8,{179,186})
DRV_DEF_F(MmuRegBlk,1,MmuIngCntDebug,cellUpdnErr,8,{171,178})
DRV_DEF_F(MmuRegBlk,1,MmuIngCntDebug,pktUpdnErr,8,{163,170})
DRV_DEF_F(MmuRegBlk,1,MmuIngCntDebug,glbCntErr,8,{155,162})
DRV_DEF_F(MmuRegBlk,1,MmuIngCntDebug,inportPtrfifoWrerr,8,{147,154})
DRV_DEF_F(MmuRegBlk,1,MmuIngCntDebug,inportPtrfifoNotreadyErr,8,{139,146})
DRV_DEF_F(MmuRegBlk,1,MmuIngCntDebug,ingPtrLenErr,8,{131,138})
DRV_DEF_F(MmuRegBlk,1,MmuIngCntDebug,reserved0,6,{125,130})
DRV_DEF_F(MmuRegBlk,1,MmuIngCntDebug,enqueueWrErr,29,{96,124})
DRV_DEF_F(MmuRegBlk,1,MmuIngCntDebug,enqZeroDrop,32,{64,95})
DRV_DEF_F(MmuRegBlk,1,MmuIngCntDebug,ipeDrop,32,{32,63})
DRV_DEF_F(MmuRegBlk,1,MmuIngCntDebug,ingPtrFullDrop,32,{0,31})

DRV_DEF_D(MmuRegBlk,1,MmuPortDebug,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x000800a4)
DRV_DEF_F(MmuRegBlk,1,MmuPortDebug,bpDis,1,{0,0})

DRV_DEF_D(MmuRegBlk,1,MmuScheduleDebug,0x0010,OP_DIRECT,TBL_SRAM,1,4,0x000800e0)
DRV_DEF_F(MmuRegBlk,1,MmuScheduleDebug,portQueueEmpty,8,{120,127})
DRV_DEF_F(MmuRegBlk,1,MmuScheduleDebug,schInfoStruct,56,{64,119})
DRV_DEF_F(MmuRegBlk,1,MmuScheduleDebug,egportShapeInprofile,32,{32,63})
DRV_DEF_F(MmuRegBlk,1,MmuScheduleDebug,portIsEmpty,32,{0,31})

DRV_DEF_D(MmuRegBlk,1,IngressMmuMib,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x000800c0)
DRV_DEF_F(MmuRegBlk,1,IngressMmuMib,mibCmdChn,5,{3,7})
DRV_DEF_F(MmuRegBlk,1,IngressMmuMib,mibCmdDir,1,{2,2})
DRV_DEF_F(MmuRegBlk,1,IngressMmuMib,mibCmd,1,{1,1})
DRV_DEF_F(MmuRegBlk,1,IngressMmuMib,mibCmdEn,1,{0,0})

DRV_DEF_SDK_D(MmuRegBlk,1,EgMonitorCtrl,0x0010,OP_DIRECT,TBL_SRAM,1,1,0x00081000)
DRV_DEF_SDK_F(MmuRegBlk,1,EgMonitorCtrl,monQMode,2,{17,18})
DRV_DEF_SDK_F(MmuRegBlk,1,EgMonitorCtrl,monMode,1,{16,16})
DRV_DEF_SDK_F(MmuRegBlk,1,EgMonitorCtrl,monPid,6,{10,15})
DRV_DEF_SDK_F(MmuRegBlk,1,EgMonitorCtrl,monQid,10,{0,9})

DRV_DEF_SDK_D(MmuRegBlk,1,EgMonPortCnt,0x0010,OP_DIRECT,TBL_SRAM,1,2,0x00081020)
DRV_DEF_SDK_F(MmuRegBlk,1,EgMonPortCnt,totalCnt,12,{27,38})
DRV_DEF_SDK_F(MmuRegBlk,1,EgMonPortCnt,yellowCnt,12,{15,26})
DRV_DEF_SDK_F(MmuRegBlk,1,EgMonPortCnt,redCnt,12,{3,14})
DRV_DEF_SDK_F(MmuRegBlk,1,EgMonPortCnt,minState,1,{2,2})
DRV_DEF_SDK_F(MmuRegBlk,1,EgMonPortCnt,dropState,2,{0,1})

DRV_DEF_SDK_D(MmuRegBlk,1,EgMonQueueCnt,0x0010,OP_DIRECT,TBL_SRAM,1,2,0x00081030)
DRV_DEF_SDK_F(MmuRegBlk,1,EgMonQueueCnt,shareucCnt,12,{39,50})
DRV_DEF_SDK_F(MmuRegBlk,1,EgMonQueueCnt,totalCnt,12,{27,38})
DRV_DEF_SDK_F(MmuRegBlk,1,EgMonQueueCnt,yellowCnt,12,{15,26})
DRV_DEF_SDK_F(MmuRegBlk,1,EgMonQueueCnt,redCnt,12,{3,14})
DRV_DEF_SDK_F(MmuRegBlk,1,EgMonQueueCnt,minState,1,{2,2})
DRV_DEF_SDK_F(MmuRegBlk,1,EgMonQueueCnt,dropState,2,{0,1})

DRV_DEF_SDK_D(MmuRegBlk,1,EgMmuGlbCtrl,0x0010,OP_DIRECT,TBL_SRAM,1,2,0x00081040)
DRV_DEF_SDK_F(MmuRegBlk,1,EgMmuGlbCtrl,shareThd,9,{45,53})
DRV_DEF_SDK_F(MmuRegBlk,1,EgMmuGlbCtrl,offsetThd,9,{36,44})
DRV_DEF_SDK_F(MmuRegBlk,1,EgMmuGlbCtrl,limitYellowThd,9,{27,35})
DRV_DEF_SDK_F(MmuRegBlk,1,EgMmuGlbCtrl,offsetYellowThd,9,{18,26})
DRV_DEF_SDK_F(MmuRegBlk,1,EgMmuGlbCtrl,limitRedThd,9,{9,17})
DRV_DEF_SDK_F(MmuRegBlk,1,EgMmuGlbCtrl,offsetRedThd,9,{0,8})

DRV_DEF_SDK_D(MmuRegBlk,1,EgMmuGlbState,0x0008,OP_DIRECT,TBL_SRAM,1,2,0x00081050)
DRV_DEF_SDK_F(MmuRegBlk,1,EgMmuGlbState,totalCnt,12,{38,49})
DRV_DEF_SDK_F(MmuRegBlk,1,EgMmuGlbState,shareCnt,12,{26,37})
DRV_DEF_SDK_F(MmuRegBlk,1,EgMmuGlbState,yellowCnt,12,{14,25})
DRV_DEF_SDK_F(MmuRegBlk,1,EgMmuGlbState,redCnt,12,{2,13})
DRV_DEF_SDK_F(MmuRegBlk,1,EgMmuGlbState,dropState,2,{0,1})

DRV_DEF_SDK_D(MmuRegBlk,1,PCellMinProfile,0x0004,OP_DIRECT,TBL_SRAM,8,1,0x00081400)
DRV_DEF_SDK_F(MmuRegBlk,1,PCellMinProfile,minThd,9,{0,8})

DRV_DEF_SDK_D(MmuRegBlk,1,PCellShareProfile,0x0004,OP_DIRECT,TBL_SRAM,8,1,0x00081500)
DRV_DEF_SDK_F(MmuRegBlk,1,PCellShareProfile,shareThd,9,{0,8})

DRV_DEF_SDK_D(MmuRegBlk,1,PCellOffsetProfile,0x0004,OP_DIRECT,TBL_SRAM,8,1,0x00081540)
DRV_DEF_SDK_F(MmuRegBlk,1,PCellOffsetProfile,offset,9,{0,8})

DRV_DEF_SDK_D(MmuRegBlk,1,PCellLimitYellowProfile,0x0004,OP_DIRECT,TBL_SRAM,8,1,0x00081580)
DRV_DEF_SDK_F(MmuRegBlk,1,PCellLimitYellowProfile,thd,9,{0,8})

DRV_DEF_SDK_D(MmuRegBlk,1,PCellOffsetYellowProfile,0x0004,OP_DIRECT,TBL_SRAM,8,1,0x000815c0)
DRV_DEF_SDK_F(MmuRegBlk,1,PCellOffsetYellowProfile,offset,9,{0,8})

DRV_DEF_SDK_D(MmuRegBlk,1,PCellLimitRedProfile,0x0004,OP_DIRECT,TBL_SRAM,8,1,0x00081600)
DRV_DEF_SDK_F(MmuRegBlk,1,PCellLimitRedProfile,thd,9,{0,8})

DRV_DEF_SDK_D(MmuRegBlk,1,PCellOffsetRedProfile,0x0004,OP_DIRECT,TBL_SRAM,8,1,0x00081640)
DRV_DEF_SDK_F(MmuRegBlk,1,PCellOffsetRedProfile,offset,9,{0,8})

DRV_DEF_SDK_D(MmuRegBlk,1,EgPortThdCtrl,0x0004,OP_DIRECT,TBL_SRAM,29,1,0x00081700)
DRV_DEF_SDK_F(MmuRegBlk,1,EgPortThdCtrl,minIndex,3,{18,20})
DRV_DEF_SDK_F(MmuRegBlk,1,EgPortThdCtrl,shareIndex,3,{15,17})
DRV_DEF_SDK_F(MmuRegBlk,1,EgPortThdCtrl,offsetIndex,3,{12,14})
DRV_DEF_SDK_F(MmuRegBlk,1,EgPortThdCtrl,yellowLimitIndex,3,{9,11})
DRV_DEF_SDK_F(MmuRegBlk,1,EgPortThdCtrl,redLimitIndex,3,{6,8})
DRV_DEF_SDK_F(MmuRegBlk,1,EgPortThdCtrl,yellowResetIndex,3,{3,5})
DRV_DEF_SDK_F(MmuRegBlk,1,EgPortThdCtrl,redResetIndex,3,{0,2})

DRV_DEF_SDK_D(MmuRegBlk,1,QCellMinProfile,0x0004,OP_DIRECT,TBL_SRAM,16,1,0x00081c00)
DRV_DEF_SDK_F(MmuRegBlk,1,QCellMinProfile,minThd,9,{0,8})

DRV_DEF_SDK_D(MmuRegBlk,1,QCellShareProfile,0x0004,OP_DIRECT,TBL_SRAM,16,1,0x00081d00)
DRV_DEF_SDK_F(MmuRegBlk,1,QCellShareProfile,shareThd,9,{1,9})
DRV_DEF_SDK_F(MmuRegBlk,1,QCellShareProfile,dynamicEn,1,{0,0})

DRV_DEF_SDK_D(MmuRegBlk,1,QCellOffsetProfile,0x0004,OP_DIRECT,TBL_SRAM,16,1,0x00081d80)
DRV_DEF_SDK_F(MmuRegBlk,1,QCellOffsetProfile,offset,9,{0,8})

DRV_DEF_SDK_D(MmuRegBlk,1,QCellLimitYellowProfile,0x0004,OP_DIRECT,TBL_SRAM,8,1,0x00081e00)
DRV_DEF_SDK_F(MmuRegBlk,1,QCellLimitYellowProfile,thd,9,{0,8})

DRV_DEF_D(MmuRegBlk,1,QCellOffsetYellowProfile,0x0004,OP_DIRECT,TBL_SRAM,8,1,0x00081e80)
DRV_DEF_F(MmuRegBlk,1,QCellOffsetYellowProfile,offset,9,{0,8})

DRV_DEF_SDK_D(MmuRegBlk,1,QCellLimitRedProfile,0x0004,OP_DIRECT,TBL_SRAM,8,1,0x00081f00)
DRV_DEF_SDK_F(MmuRegBlk,1,QCellLimitRedProfile,thd,9,{0,8})

DRV_DEF_D(MmuRegBlk,1,QCellOffsetRedProfile,0x0004,OP_DIRECT,TBL_SRAM,8,1,0x00081f80)
DRV_DEF_F(MmuRegBlk,1,QCellOffsetRedProfile,offset,9,{0,8})

DRV_DEF_D(MmuRegBlk,1,EgQueueThdCtrl,0x0004,OP_DIRECT,TBL_SRAM,272,1,0x00082000)
DRV_DEF_F(MmuRegBlk,1,EgQueueThdCtrl,minIndex,4,{20,23})
DRV_DEF_F(MmuRegBlk,1,EgQueueThdCtrl,shareIndex,4,{16,19})
DRV_DEF_F(MmuRegBlk,1,EgQueueThdCtrl,offsetIndex,4,{12,15})
DRV_DEF_F(MmuRegBlk,1,EgQueueThdCtrl,yellowLimitIndex,3,{9,11})
DRV_DEF_F(MmuRegBlk,1,EgQueueThdCtrl,redLimitIndex,3,{6,8})
DRV_DEF_F(MmuRegBlk,1,EgQueueThdCtrl,yellowResetIndex,3,{3,5})
DRV_DEF_F(MmuRegBlk,1,EgQueueThdCtrl,redResetIndex,3,{0,2})

DRV_DEF_SDK_D(MmuRegBlk,1,PortShape,0x0008,OP_DIRECT,TBL_SRAM,29,2,0x00083000)
DRV_DEF_SDK_F(MmuRegBlk,1,PortShape,meterMode,1,{35,35})
DRV_DEF_SDK_F(MmuRegBlk,1,PortShape,meterGrain,3,{32,34})
DRV_DEF_SDK_F(MmuRegBlk,1,PortShape,maxRefreshCnt,19,{13,31})
DRV_DEF_SDK_F(MmuRegBlk,1,PortShape,maxThreshold,12,{1,12})
DRV_DEF_SDK_F(MmuRegBlk,1,PortShape,maxMeterEn,1,{0,0})

DRV_DEF_SDK_D(MmuRegBlk,1,SchPortMode,0x0004,OP_DIRECT,TBL_SRAM,29,1,0x00083100)
DRV_DEF_SDK_F(MmuRegBlk,1,SchPortMode,quanta,2,{9,10})
DRV_DEF_SDK_F(MmuRegBlk,1,SchPortMode,wrrMode,1,{8,8})
DRV_DEF_SDK_F(MmuRegBlk,1,SchPortMode,spBitmap,8,{0,7})

DRV_DEF_SDK_D(MmuRegBlk,1,SchGlbMode,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x00083200)
DRV_DEF_SDK_F(MmuRegBlk,1,SchGlbMode,minMaxIfgBytes,5,{6,10})
DRV_DEF_SDK_F(MmuRegBlk,1,SchGlbMode,ifgBytes,5,{1,5})
DRV_DEF_SDK_F(MmuRegBlk,1,SchGlbMode,ituMode,1,{0,0})

DRV_DEF_M(PeMemBlk,1)
DRV_DEF_SDK_D(PeMemBlk,1,IngressMstpTable,0x0010,OP_DIRECT,TBL_SRAM,32,3,0x00200800)
DRV_DEF_SDK_F(PeMemBlk,1,IngressMstpTable,stpStPort28,3,{88,90})
DRV_DEF_SDK_F(PeMemBlk,1,IngressMstpTable,stpStPort27,3,{85,87})
DRV_DEF_SDK_F(PeMemBlk,1,IngressMstpTable,stpStPort26,3,{82,84})
DRV_DEF_SDK_F(PeMemBlk,1,IngressMstpTable,stpStPort25,3,{79,81})
DRV_DEF_SDK_F(PeMemBlk,1,IngressMstpTable,stpStPort24,3,{76,78})
DRV_DEF_SDK_F(PeMemBlk,1,IngressMstpTable,stpStPort23,3,{73,75})
DRV_DEF_SDK_F(PeMemBlk,1,IngressMstpTable,stpStPort22,3,{70,72})
DRV_DEF_SDK_F(PeMemBlk,1,IngressMstpTable,stpStPort21,3,{67,69})
DRV_DEF_SDK_F(PeMemBlk,1,IngressMstpTable,stpStPort20,3,{64,66})
DRV_DEF_SDK_F(PeMemBlk,1,IngressMstpTable,stpStPort19,3,{59,61})
DRV_DEF_SDK_F(PeMemBlk,1,IngressMstpTable,stpStPort18,3,{56,58})
DRV_DEF_SDK_F(PeMemBlk,1,IngressMstpTable,stpStPort17,3,{53,55})
DRV_DEF_SDK_F(PeMemBlk,1,IngressMstpTable,stpStPort16,3,{50,52})
DRV_DEF_SDK_F(PeMemBlk,1,IngressMstpTable,stpStPort15,3,{47,49})
DRV_DEF_SDK_F(PeMemBlk,1,IngressMstpTable,stpStPort14,3,{44,46})
DRV_DEF_SDK_F(PeMemBlk,1,IngressMstpTable,stpStPort13,3,{41,43})
DRV_DEF_SDK_F(PeMemBlk,1,IngressMstpTable,stpStPort12,3,{38,40})
DRV_DEF_SDK_F(PeMemBlk,1,IngressMstpTable,stpStPort11,3,{35,37})
DRV_DEF_SDK_F(PeMemBlk,1,IngressMstpTable,stpStPort10,3,{32,34})
DRV_DEF_SDK_F(PeMemBlk,1,IngressMstpTable,stpStPort9,3,{27,29})
DRV_DEF_SDK_F(PeMemBlk,1,IngressMstpTable,stpStPort8,3,{24,26})
DRV_DEF_SDK_F(PeMemBlk,1,IngressMstpTable,stpStPort7,3,{21,23})
DRV_DEF_SDK_F(PeMemBlk,1,IngressMstpTable,stpStPort6,3,{18,20})
DRV_DEF_SDK_F(PeMemBlk,1,IngressMstpTable,stpStPort5,3,{15,17})
DRV_DEF_SDK_F(PeMemBlk,1,IngressMstpTable,stpStPort4,3,{12,14})
DRV_DEF_SDK_F(PeMemBlk,1,IngressMstpTable,stpStPort3,3,{9,11})
DRV_DEF_SDK_F(PeMemBlk,1,IngressMstpTable,stpStPort2,3,{6,8})
DRV_DEF_SDK_F(PeMemBlk,1,IngressMstpTable,stpStPort1,3,{3,5})
DRV_DEF_SDK_F(PeMemBlk,1,IngressMstpTable,stpStPort0,3,{0,2})
DRV_DEF_SDK_F(PeMemBlk,1,IngressMstpTable,reserved1,2,{30,31})
DRV_DEF_SDK_F(PeMemBlk,1,IngressMstpTable,reserved0,2,{62,63})

DRV_DEF_SDK_D(PeMemBlk,1,EgressMstpTable,0x0004,OP_DIRECT,TBL_SRAM,32,1,0x00291900)
DRV_DEF_SDK_F(PeMemBlk,1,EgressMstpTable,stpStPort28,1,{28,28})
DRV_DEF_SDK_F(PeMemBlk,1,EgressMstpTable,stpStPort27,1,{27,27})
DRV_DEF_SDK_F(PeMemBlk,1,EgressMstpTable,stpStPort26,1,{26,26})
DRV_DEF_SDK_F(PeMemBlk,1,EgressMstpTable,stpStPort25,1,{25,25})
DRV_DEF_SDK_F(PeMemBlk,1,EgressMstpTable,stpStPort24,1,{24,24})
DRV_DEF_SDK_F(PeMemBlk,1,EgressMstpTable,stpStPort23,1,{23,23})
DRV_DEF_SDK_F(PeMemBlk,1,EgressMstpTable,stpStPort22,1,{22,22})
DRV_DEF_SDK_F(PeMemBlk,1,EgressMstpTable,stpStPort21,1,{21,21})
DRV_DEF_SDK_F(PeMemBlk,1,EgressMstpTable,stpStPort20,1,{20,20})
DRV_DEF_SDK_F(PeMemBlk,1,EgressMstpTable,stpStPort19,1,{19,19})
DRV_DEF_SDK_F(PeMemBlk,1,EgressMstpTable,stpStPort18,1,{18,18})
DRV_DEF_SDK_F(PeMemBlk,1,EgressMstpTable,stpStPort17,1,{17,17})
DRV_DEF_SDK_F(PeMemBlk,1,EgressMstpTable,stpStPort16,1,{16,16})
DRV_DEF_SDK_F(PeMemBlk,1,EgressMstpTable,stpStPort15,1,{15,15})
DRV_DEF_SDK_F(PeMemBlk,1,EgressMstpTable,stpStPort14,1,{14,14})
DRV_DEF_SDK_F(PeMemBlk,1,EgressMstpTable,stpStPort13,1,{13,13})
DRV_DEF_SDK_F(PeMemBlk,1,EgressMstpTable,stpStPort12,1,{12,12})
DRV_DEF_SDK_F(PeMemBlk,1,EgressMstpTable,stpStPort11,1,{11,11})
DRV_DEF_SDK_F(PeMemBlk,1,EgressMstpTable,stpStPort10,1,{10,10})
DRV_DEF_SDK_F(PeMemBlk,1,EgressMstpTable,stpStPort9,1,{9,9})
DRV_DEF_SDK_F(PeMemBlk,1,EgressMstpTable,stpStPort8,1,{8,8})
DRV_DEF_SDK_F(PeMemBlk,1,EgressMstpTable,stpStPort7,1,{7,7})
DRV_DEF_SDK_F(PeMemBlk,1,EgressMstpTable,stpStPort6,1,{6,6})
DRV_DEF_SDK_F(PeMemBlk,1,EgressMstpTable,stpStPort5,1,{5,5})
DRV_DEF_SDK_F(PeMemBlk,1,EgressMstpTable,stpStPort4,1,{4,4})
DRV_DEF_SDK_F(PeMemBlk,1,EgressMstpTable,stpStPort3,1,{3,3})
DRV_DEF_SDK_F(PeMemBlk,1,EgressMstpTable,stpStPort2,1,{2,2})
DRV_DEF_SDK_F(PeMemBlk,1,EgressMstpTable,stpStPort1,1,{1,1})
DRV_DEF_SDK_F(PeMemBlk,1,EgressMstpTable,stpStPort0,1,{0,0})

DRV_DEF_SDK_D(PeMemBlk,1,IresolutionDropMib,0x0004,OP_INDIRECT,TBL_SRAM,1024,1,0x0031e000)
DRV_DEF_SDK_F(PeMemBlk,1,IresolutionDropMib,frameCnt,32,{0,31})

DRV_DEF_SDK_D(PeMemBlk,1,EresolutionDropMib,0x0004,OP_INDIRECT,TBL_SRAM,256,1,0x0031f000)
DRV_DEF_SDK_F(PeMemBlk,1,EresolutionDropMib,frameCnt,32,{0,31})

DRV_DEF_D(PeMemBlk,1,IngressPtagData,0x0010,OP_DIRECT,TBL_SRAM,1,4,0x00200000)
DRV_DEF_F(PeMemBlk,1,IngressPtagData,opcode,3,{109,111})
DRV_DEF_F(PeMemBlk,1,IngressPtagData,inserviceMeterId,11,{98,108})
DRV_DEF_F(PeMemBlk,1,IngressPtagData,inserviceMeterDir,1,{97,97})
DRV_DEF_F(PeMemBlk,1,IngressPtagData,inserviceMeterMode,1,{96,96})
DRV_DEF_F(PeMemBlk,1,IngressPtagData,isInservice,1,{95,95})
DRV_DEF_F(PeMemBlk,1,IngressPtagData,oamY1564,1,{94,94})
DRV_DEF_F(PeMemBlk,1,IngressPtagData,oamPortBased,1,{93,93})
DRV_DEF_F(PeMemBlk,1,IngressPtagData,tsInsert,3,{90,92})
DRV_DEF_F(PeMemBlk,1,IngressPtagData,ts1588cf,2,{88,89})
DRV_DEF_F(PeMemBlk,1,IngressPtagData,tsAddtail,2,{86,87})
DRV_DEF_F(PeMemBlk,1,IngressPtagData,tsMode,2,{84,85})
DRV_DEF_F(PeMemBlk,1,IngressPtagData,tscntOffset,8,{76,83})
DRV_DEF_F(PeMemBlk,1,IngressPtagData,cntInsert,3,{73,75})
DRV_DEF_F(PeMemBlk,1,IngressPtagData,cntAddtail,2,{71,72})
DRV_DEF_F(PeMemBlk,1,IngressPtagData,cntMode,2,{69,70})
DRV_DEF_F(PeMemBlk,1,IngressPtagData,cntIndex,10,{59,68})
DRV_DEF_F(PeMemBlk,1,IngressPtagData,notModify,1,{58,58})
DRV_DEF_F(PeMemBlk,1,IngressPtagData,useThisQpdp,1,{57,57})
DRV_DEF_F(PeMemBlk,1,IngressPtagData,qpdp,6,{51,56})
DRV_DEF_F(PeMemBlk,1,IngressPtagData,fid,12,{39,50})
DRV_DEF_F(PeMemBlk,1,IngressPtagData,bitmapMode,1,{38,38})
DRV_DEF_F(PeMemBlk,1,IngressPtagData,reserved0,1,{37,37})
DRV_DEF_F(PeMemBlk,1,IngressPtagData,bypassEgmeter,1,{36,36})
DRV_DEF_F(PeMemBlk,1,IngressPtagData,reserved1,1,{35,35})
DRV_DEF_F(PeMemBlk,1,IngressPtagData,bypassEgloopback,1,{34,34})
DRV_DEF_F(PeMemBlk,1,IngressPtagData,bypassEgstp,1,{33,33})
DRV_DEF_F(PeMemBlk,1,IngressPtagData,bypassEgvlan,1,{32,32})
DRV_DEF_F(PeMemBlk,1,IngressPtagData,reserved2,2,{30,31})
DRV_DEF_F(PeMemBlk,1,IngressPtagData,bypassEgacl,1,{29,29})
DRV_DEF_F(PeMemBlk,1,IngressPtagData,bypassIsvid,1,{28,28})
DRV_DEF_F(PeMemBlk,1,IngressPtagData,bypassEap,1,{27,27})
DRV_DEF_F(PeMemBlk,1,IngressPtagData,bypassInmeter,1,{26,26})
DRV_DEF_F(PeMemBlk,1,IngressPtagData,bypassInprotect,1,{25,25})
DRV_DEF_F(PeMemBlk,1,IngressPtagData,bypassInloopback,1,{24,24})
DRV_DEF_F(PeMemBlk,1,IngressPtagData,bypassInstp,1,{23,23})
DRV_DEF_F(PeMemBlk,1,IngressPtagData,bypassInvlan,1,{22,22})
DRV_DEF_F(PeMemBlk,1,IngressPtagData,bypassLearning,1,{21,21})
DRV_DEF_F(PeMemBlk,1,IngressPtagData,bypassInspmac,1,{20,20})
DRV_DEF_F(PeMemBlk,1,IngressPtagData,bypassInacl,1,{19,19})
DRV_DEF_F(PeMemBlk,1,IngressPtagData,portMode,2,{17,18})
DRV_DEF_F(PeMemBlk,1,IngressPtagData,portBitmapL,17,{0,16})

DRV_DEF_D(PeMemBlk,1,EgressPtagData,0x0010,OP_DIRECT,TBL_SRAM,1,4,0x00200000)
DRV_DEF_F(PeMemBlk,1,EgressPtagData,reserved0,1,{111,111})
DRV_DEF_F(PeMemBlk,1,EgressPtagData,cntIndex,10,{101,110})
DRV_DEF_F(PeMemBlk,1,EgressPtagData,dportBitmap,26,{75,100})
DRV_DEF_F(PeMemBlk,1,EgressPtagData,internalSvid,12,{63,74})
DRV_DEF_F(PeMemBlk,1,EgressPtagData,localColor,2,{61,62})
DRV_DEF_F(PeMemBlk,1,EgressPtagData,localPri,4,{57,60})
DRV_DEF_F(PeMemBlk,1,EgressPtagData,qp,3,{54,56})
DRV_DEF_F(PeMemBlk,1,EgressPtagData,notLearning,1,{53,53})
DRV_DEF_F(PeMemBlk,1,EgressPtagData,ivtChkFailTocpu,1,{52,52})
DRV_DEF_F(PeMemBlk,1,EgressPtagData,ivtUnknownTocpu,1,{51,51})
DRV_DEF_F(PeMemBlk,1,EgressPtagData,ipHaveOption,1,{50,50})
DRV_DEF_F(PeMemBlk,1,EgressPtagData,egmirTocpu,1,{49,49})
DRV_DEF_F(PeMemBlk,1,EgressPtagData,ingmirTocpu,1,{48,48})
DRV_DEF_F(PeMemBlk,1,EgressPtagData,aclTocpu,1,{47,47})
DRV_DEF_F(PeMemBlk,1,EgressPtagData,pmacTocpu,1,{46,46})
DRV_DEF_F(PeMemBlk,1,EgressPtagData,smacTocpu,1,{45,45})
DRV_DEF_F(PeMemBlk,1,EgressPtagData,ptpTocpu,1,{44,44})
DRV_DEF_F(PeMemBlk,1,EgressPtagData,oamTocpu,2,{42,43})
DRV_DEF_F(PeMemBlk,1,EgressPtagData,cpuPtagTocpu,1,{41,41})
DRV_DEF_F(PeMemBlk,1,EgressPtagData,oamPtagTocpu,1,{40,40})
DRV_DEF_F(PeMemBlk,1,EgressPtagData,arlCpucopy,4,{36,39})
DRV_DEF_F(PeMemBlk,1,EgressPtagData,srcPort,6,{30,35})
DRV_DEF_F(PeMemBlk,1,EgressPtagData,spmacIndexVld,1,{29,29})
DRV_DEF_F(PeMemBlk,1,EgressPtagData,aclIndexVld,1,{28,28})
DRV_DEF_F(PeMemBlk,1,EgressPtagData,aclIndex,8,{20,27})
DRV_DEF_F(PeMemBlk,1,EgressPtagData,tsMode,2,{18,19})
DRV_DEF_F(PeMemBlk,1,EgressPtagData,tailTs,1,{17,17})
DRV_DEF_F(PeMemBlk,1,EgressPtagData,tailCnt,1,{16,16})
DRV_DEF_F(PeMemBlk,1,EgressPtagData,itagStatus,2,{14,15})
DRV_DEF_F(PeMemBlk,1,EgressPtagData,otagAction,2,{12,13})
DRV_DEF_F(PeMemBlk,1,EgressPtagData,itagAction,2,{10,11})
DRV_DEF_F(PeMemBlk,1,EgressPtagData,oam1588Type,2,{8,9})
DRV_DEF_F(PeMemBlk,1,EgressPtagData,ipType,2,{6,7})
DRV_DEF_F(PeMemBlk,1,EgressPtagData,layerType,3,{3,5})
DRV_DEF_F(PeMemBlk,1,EgressPtagData,vlanNum,3,{0,2})

DRV_DEF_SDK_D(PeMemBlk,1,SmacAct,0x0008,OP_DIRECT,TBL_SRAM,608,2,0x00202000)
DRV_DEF_SDK_F(PeMemBlk,1,SmacAct,valid,1,{58,58})
DRV_DEF_SDK_F(PeMemBlk,1,SmacAct,qp2cpu,6,{52,57})
DRV_DEF_SDK_F(PeMemBlk,1,SmacAct,changeQp2cpu,1,{51,51})
DRV_DEF_SDK_F(PeMemBlk,1,SmacAct,daChange,1,{50,50})
DRV_DEF_SDK_F(PeMemBlk,1,SmacAct,notModify,1,{49,49})
DRV_DEF_SDK_F(PeMemBlk,1,SmacAct,tagMode,2,{47,48})
DRV_DEF_SDK_F(PeMemBlk,1,SmacAct,bypassLoopback,1,{46,46})
DRV_DEF_SDK_F(PeMemBlk,1,SmacAct,bypassProtect,1,{45,45})
DRV_DEF_SDK_F(PeMemBlk,1,SmacAct,bypassLearnDrop,1,{44,44})
DRV_DEF_SDK_F(PeMemBlk,1,SmacAct,bypassStp,1,{43,43})
DRV_DEF_SDK_F(PeMemBlk,1,SmacAct,bypassEvcDrop,1,{42,42})
DRV_DEF_SDK_F(PeMemBlk,1,SmacAct,bypassEapDrop,1,{41,41})
DRV_DEF_SDK_F(PeMemBlk,1,SmacAct,bypassLearning,1,{40,40})
DRV_DEF_SDK_F(PeMemBlk,1,SmacAct,bypassVlanCheck,1,{39,39})
DRV_DEF_SDK_F(PeMemBlk,1,SmacAct,mirrorEn,1,{38,38})
DRV_DEF_SDK_F(PeMemBlk,1,SmacAct,drop,1,{37,37})
DRV_DEF_SDK_F(PeMemBlk,1,SmacAct,copyToCpu,1,{36,36})
DRV_DEF_SDK_F(PeMemBlk,1,SmacAct,redirectPortBitmap,29,{7,35})
DRV_DEF_SDK_F(PeMemBlk,1,SmacAct,redirectLagBitmap,5,{2,6})
DRV_DEF_SDK_F(PeMemBlk,1,SmacAct,redirectEnable,1,{1,1})
DRV_DEF_SDK_F(PeMemBlk,1,SmacAct,bitmapMode,1,{0,0})

DRV_DEF_SDK_D(PeMemBlk,1,PmacAct,0x0008,OP_DIRECT,TBL_SRAM,256,2,0x00207000)
DRV_DEF_SDK_F(PeMemBlk,1,PmacAct,valid,1,{58,58})
DRV_DEF_SDK_F(PeMemBlk,1,PmacAct,qp2cpu,6,{52,57})
DRV_DEF_SDK_F(PeMemBlk,1,PmacAct,changeQp2cpu,1,{51,51})
DRV_DEF_SDK_F(PeMemBlk,1,PmacAct,daChange,1,{50,50})
DRV_DEF_SDK_F(PeMemBlk,1,PmacAct,notModify,1,{49,49})
DRV_DEF_SDK_F(PeMemBlk,1,PmacAct,tagMode,2,{47,48})
DRV_DEF_SDK_F(PeMemBlk,1,PmacAct,bypassLoopback,1,{46,46})
DRV_DEF_SDK_F(PeMemBlk,1,PmacAct,bypassProtect,1,{45,45})
DRV_DEF_SDK_F(PeMemBlk,1,PmacAct,bypassLearnDrop,1,{44,44})
DRV_DEF_SDK_F(PeMemBlk,1,PmacAct,bypassStp,1,{43,43})
DRV_DEF_SDK_F(PeMemBlk,1,PmacAct,bypassEvcDrop,1,{42,42})
DRV_DEF_SDK_F(PeMemBlk,1,PmacAct,bypassEapDrop,1,{41,41})
DRV_DEF_SDK_F(PeMemBlk,1,PmacAct,bypassLearning,1,{40,40})
DRV_DEF_SDK_F(PeMemBlk,1,PmacAct,bypassVlanCheck,1,{39,39})
DRV_DEF_SDK_F(PeMemBlk,1,PmacAct,mirrorEn,1,{38,38})
DRV_DEF_SDK_F(PeMemBlk,1,PmacAct,drop,1,{37,37})
DRV_DEF_SDK_F(PeMemBlk,1,PmacAct,copyToCpu,1,{36,36})
DRV_DEF_SDK_F(PeMemBlk,1,PmacAct,redirectPortBitmap,29,{7,35})
DRV_DEF_SDK_F(PeMemBlk,1,PmacAct,redirectLagBitmap,5,{2,6})
DRV_DEF_SDK_F(PeMemBlk,1,PmacAct,redirectEnable,1,{1,1})
DRV_DEF_SDK_F(PeMemBlk,1,PmacAct,bitmapMode,1,{0,0})

DRV_DEF_SDK_D(PeMemBlk,1,IvmXIndex,0x0004,OP_DIRECT,TBL_SRAM,16,1,0x0020af00)
DRV_DEF_SDK_F(PeMemBlk,1,IvmXIndex,ivmIndex,12,{0,11})

DRV_DEF_SDK_D(PeMemBlk,1,IvmTable,0x0010,OP_DIRECT,TBL_SRAM,298,3,0x00240000)
DRV_DEF_SDK_F(PeMemBlk,1,IvmTable,valid,1,{79,79})
DRV_DEF_SDK_F(PeMemBlk,1,IvmTable,counterIndex,10,{69,78})
DRV_DEF_SDK_F(PeMemBlk,1,IvmTable,counterEnable,1,{68,68})
DRV_DEF_SDK_F(PeMemBlk,1,IvmTable,mirrorEn,1,{67,67})
DRV_DEF_SDK_F(PeMemBlk,1,IvmTable,drop,1,{66,66})
DRV_DEF_SDK_F(PeMemBlk,1,IvmTable,bypassVlanCheck,1,{65,65})
DRV_DEF_SDK_F(PeMemBlk,1,IvmTable,bypassStp,1,{64,64})
DRV_DEF_SDK_F(PeMemBlk,1,IvmTable,swapTag,1,{63,63})
DRV_DEF_SDK_F(PeMemBlk,1,IvmTable,tagActionProfilePtr,5,{58,62})
DRV_DEF_SDK_F(PeMemBlk,1,IvmTable,isvidMode,1,{57,57})
DRV_DEF_SDK_F(PeMemBlk,1,IvmTable,policeIndex,6,{51,56})
DRV_DEF_SDK_F(PeMemBlk,1,IvmTable,policeMode,1,{50,50})
DRV_DEF_SDK_F(PeMemBlk,1,IvmTable,trustPriMode,2,{48,49})
DRV_DEF_SDK_F(PeMemBlk,1,IvmTable,priIndex,4,{44,47})
DRV_DEF_SDK_F(PeMemBlk,1,IvmTable,remarkDscpMode,2,{42,43})
DRV_DEF_SDK_F(PeMemBlk,1,IvmTable,remarkDscp,6,{36,41})
DRV_DEF_SDK_F(PeMemBlk,1,IvmTable,remarkScosMode,2,{34,35})
DRV_DEF_SDK_F(PeMemBlk,1,IvmTable,remarkCcosMode,2,{32,33})
DRV_DEF_SDK_F(PeMemBlk,1,IvmTable,remarkScos,4,{28,31})
DRV_DEF_SDK_F(PeMemBlk,1,IvmTable,remarkCcos,4,{24,27})
DRV_DEF_SDK_F(PeMemBlk,1,IvmTable,svid,12,{12,23})
DRV_DEF_SDK_F(PeMemBlk,1,IvmTable,cvid,12,{0,11})

DRV_DEF_SDK_D(PeMemBlk,1,IvmActionProfile,0x0004,OP_DIRECT,TBL_SRAM,32,1,0x00250000)
DRV_DEF_SDK_F(PeMemBlk,1,IvmActionProfile,dtTagAction,4,{24,27})
DRV_DEF_SDK_F(PeMemBlk,1,IvmActionProfile,dtOpStagAction,2,{22,23})
DRV_DEF_SDK_F(PeMemBlk,1,IvmActionProfile,dtIpCtagAction,2,{20,21})
DRV_DEF_SDK_F(PeMemBlk,1,IvmActionProfile,sotTagAction,4,{16,19})
DRV_DEF_SDK_F(PeMemBlk,1,IvmActionProfile,sopTagAction,4,{12,15})
DRV_DEF_SDK_F(PeMemBlk,1,IvmActionProfile,sitTagAction,4,{8,11})
DRV_DEF_SDK_F(PeMemBlk,1,IvmActionProfile,sipTagAction,4,{4,7})
DRV_DEF_SDK_F(PeMemBlk,1,IvmActionProfile,utTagAction,4,{0,3})

DRV_DEF_SDK_D(PeMemBlk,1,IvtTable,0x0010,OP_DIRECT,TBL_SRAM,4096,3,0x00260000)
DRV_DEF_SDK_F(PeMemBlk,1,IvtTable,valid,1,{67,67})
DRV_DEF_SDK_F(PeMemBlk,1,IvtTable,noNniNniFwd,1,{66,66})
DRV_DEF_SDK_F(PeMemBlk,1,IvtTable,noUniUniFwd,1,{65,65})
DRV_DEF_SDK_F(PeMemBlk,1,IvtTable,iepp2ndHash,3,{62,64})
DRV_DEF_SDK_F(PeMemBlk,1,IvtTable,ipep2ndHash,3,{59,61})
DRV_DEF_SDK_F(PeMemBlk,1,IvtTable,fid,12,{47,58})
DRV_DEF_SDK_F(PeMemBlk,1,IvtTable,ingressMstpGroupIndex,5,{42,46})
DRV_DEF_SDK_F(PeMemBlk,1,IvtTable,vlanProfileIndex,7,{35,41})
DRV_DEF_SDK_F(PeMemBlk,1,IvtTable,nniMaster,1,{34,34})
DRV_DEF_SDK_F(PeMemBlk,1,IvtTable,protectionWorkingPath,1,{33,33})
DRV_DEF_SDK_F(PeMemBlk,1,IvtTable,protectMode,3,{30,32})
DRV_DEF_SDK_F(PeMemBlk,1,IvtTable,dropProtectPktEn,1,{29,29})
DRV_DEF_SDK_F(PeMemBlk,1,IvtTable,vlanMember,29,{0,28})

DRV_DEF_SDK_D(PeMemBlk,1,IvtProfile,0x0010,OP_DIRECT,TBL_SRAM,128,3,0x00270000)
DRV_DEF_SDK_F(PeMemBlk,1,IvtProfile,bcastMaskSel,2,{88,89})
DRV_DEF_SDK_F(PeMemBlk,1,IvtProfile,unknownUcastMaskSel,2,{86,87})
DRV_DEF_SDK_F(PeMemBlk,1,IvtProfile,knownMcastMaskSel,2,{84,85})
DRV_DEF_SDK_F(PeMemBlk,1,IvtProfile,unknownMcastMaskSel,2,{82,83})
DRV_DEF_SDK_F(PeMemBlk,1,IvtProfile,blockMaskA,29,{53,81})
DRV_DEF_SDK_F(PeMemBlk,1,IvtProfile,blockMaskB,29,{24,52})
DRV_DEF_SDK_F(PeMemBlk,1,IvtProfile,stcEn,1,{23,23})
DRV_DEF_SDK_F(PeMemBlk,1,IvtProfile,stcBaseIndex,7,{16,22})
DRV_DEF_SDK_F(PeMemBlk,1,IvtProfile,dlfStcEn,1,{15,15})
DRV_DEF_SDK_F(PeMemBlk,1,IvtProfile,mlfStcEn,1,{14,14})
DRV_DEF_SDK_F(PeMemBlk,1,IvtProfile,l2mcStcEn,1,{13,13})
DRV_DEF_SDK_F(PeMemBlk,1,IvtProfile,bcStcEn,1,{12,12})
DRV_DEF_SDK_F(PeMemBlk,1,IvtProfile,fidCfgSm,1,{11,11})
DRV_DEF_SDK_F(PeMemBlk,1,IvtProfile,fidCfgSa,1,{10,10})
DRV_DEF_SDK_F(PeMemBlk,1,IvtProfile,mlfDrop,1,{9,9})
DRV_DEF_SDK_F(PeMemBlk,1,IvtProfile,ulfDrop,1,{8,8})
DRV_DEF_SDK_F(PeMemBlk,1,IvtProfile,bcDrop,1,{7,7})
DRV_DEF_SDK_F(PeMemBlk,1,IvtProfile,stpidIndex,2,{5,6})
DRV_DEF_SDK_F(PeMemBlk,1,IvtProfile,drop,1,{4,4})
DRV_DEF_SDK_F(PeMemBlk,1,IvtProfile,priSel,1,{3,3})
DRV_DEF_SDK_F(PeMemBlk,1,IvtProfile,qosMode,1,{2,2})
DRV_DEF_SDK_F(PeMemBlk,1,IvtProfile,arlType,2,{0,1})

DRV_DEF_D(PeMemBlk,1,VlanXlate,0x0008,OP_DIRECT,TBL_HASH,256,2,0x00254000)
DRV_DEF_F(PeMemBlk,1,VlanXlate,data,44,{0,43})

DRV_DEF_SDK_D(PeMemBlk,1,XlateMacVlanKey,0x0010,OP_INDIRECT,TBL_HASH,256,3,0x00254000)
DRV_DEF_SDK_F(PeMemBlk,1,XlateMacVlanKey,ivmIndex,9,{79,87})
DRV_DEF_SDK_F(PeMemBlk,1,XlateMacVlanKey,reserved0,13,{66,78})
DRV_DEF_SDK_F(PeMemBlk,1,XlateMacVlanKey,sa,48,{18,65})
DRV_DEF_SDK_F(PeMemBlk,1,XlateMacVlanKey,svid,12,{6,17})
DRV_DEF_SDK_F(PeMemBlk,1,XlateMacVlanKey,keyType,4,{2,5})
DRV_DEF_SDK_F(PeMemBlk,1,XlateMacVlanKey,valid,2,{0,1})

DRV_DEF_SDK_D(PeMemBlk,1,XlateMacKey,0x0010,OP_INDIRECT,TBL_HASH,256,3,0x00254000)
DRV_DEF_SDK_F(PeMemBlk,1,XlateMacKey,ivmIndex,9,{79,87})
DRV_DEF_SDK_F(PeMemBlk,1,XlateMacKey,reserved0,25,{54,78})
DRV_DEF_SDK_F(PeMemBlk,1,XlateMacKey,sa,48,{6,53})
DRV_DEF_SDK_F(PeMemBlk,1,XlateMacKey,keyType,4,{2,5})
DRV_DEF_SDK_F(PeMemBlk,1,XlateMacKey,valid,2,{0,1})

DRV_DEF_SDK_D(PeMemBlk,1,XlateIpv4Key,0x0010,OP_INDIRECT,TBL_HASH,256,3,0x00254000)
DRV_DEF_SDK_F(PeMemBlk,1,XlateIpv4Key,ivmIndex,9,{79,87})
DRV_DEF_SDK_F(PeMemBlk,1,XlateIpv4Key,reserved0,35,{44,78})
DRV_DEF_SDK_F(PeMemBlk,1,XlateIpv4Key,sip,32,{12,43})
DRV_DEF_SDK_F(PeMemBlk,1,XlateIpv4Key,sport,6,{6,11})
DRV_DEF_SDK_F(PeMemBlk,1,XlateIpv4Key,keyType,4,{2,5})
DRV_DEF_SDK_F(PeMemBlk,1,XlateIpv4Key,valid,2,{0,1})

DRV_DEF_SDK_D(PeMemBlk,1,XlateIpv6Key,0x0010,OP_INDIRECT,TBL_HASH,256,6,0x00254000)
DRV_DEF_SDK_F(PeMemBlk,1,XlateIpv6Key,ivmIndex,9,{167,175})
DRV_DEF_SDK_F(PeMemBlk,1,XlateIpv6Key,reserved0,31,{136,166})
DRV_DEF_SDK_F(PeMemBlk,1,XlateIpv6Key,sip,128,{8,135})
DRV_DEF_SDK_F(PeMemBlk,1,XlateIpv6Key,keyType,4,{4,7})
DRV_DEF_SDK_F(PeMemBlk,1,XlateIpv6Key,valid,4,{0,3})

DRV_DEF_SDK_D(PeMemBlk,1,XlateSvlanKey,0x0010,OP_INDIRECT,TBL_HASH,256,2,0x00254000)
DRV_DEF_SDK_F(PeMemBlk,1,XlateSvlanKey,ivmIndex,9,{35,43})
DRV_DEF_SDK_F(PeMemBlk,1,XlateSvlanKey,reserved0,12,{23,34})
DRV_DEF_SDK_F(PeMemBlk,1,XlateSvlanKey,svid,12,{11,22})
DRV_DEF_SDK_F(PeMemBlk,1,XlateSvlanKey,sport,6,{5,10})
DRV_DEF_SDK_F(PeMemBlk,1,XlateSvlanKey,keyType,4,{1,4})
DRV_DEF_SDK_F(PeMemBlk,1,XlateSvlanKey,valid,1,{0,0})

DRV_DEF_SDK_D(PeMemBlk,1,XlateDoubleVlanKey,0x0010,OP_INDIRECT,TBL_HASH,256,2,0x00254000)
DRV_DEF_SDK_F(PeMemBlk,1,XlateDoubleVlanKey,ivmIndex,9,{35,43})
DRV_DEF_SDK_F(PeMemBlk,1,XlateDoubleVlanKey,svid,12,{23,34})
DRV_DEF_SDK_F(PeMemBlk,1,XlateDoubleVlanKey,cvid,12,{11,22})
DRV_DEF_SDK_F(PeMemBlk,1,XlateDoubleVlanKey,sport,6,{5,10})
DRV_DEF_SDK_F(PeMemBlk,1,XlateDoubleVlanKey,keyType,4,{1,4})
DRV_DEF_SDK_F(PeMemBlk,1,XlateDoubleVlanKey,valid,1,{0,0})

DRV_DEF_SDK_D(PeMemBlk,1,XlateCvlanKey,0x0010,OP_INDIRECT,TBL_HASH,256,2,0x00254000)
DRV_DEF_SDK_F(PeMemBlk,1,XlateCvlanKey,ivmIndex,9,{35,43})
DRV_DEF_SDK_F(PeMemBlk,1,XlateCvlanKey,reserved0,12,{23,34})
DRV_DEF_SDK_F(PeMemBlk,1,XlateCvlanKey,cvid,12,{11,22})
DRV_DEF_SDK_F(PeMemBlk,1,XlateCvlanKey,sport,6,{5,10})
DRV_DEF_SDK_F(PeMemBlk,1,XlateCvlanKey,keyType,4,{1,4})
DRV_DEF_SDK_F(PeMemBlk,1,XlateCvlanKey,valid,1,{0,0})

DRV_DEF_SDK_D(PeMemBlk,1,XlateOtagKey,0x0010,OP_INDIRECT,TBL_HASH,256,2,0x00254000)
DRV_DEF_SDK_F(PeMemBlk,1,XlateOtagKey,ivmIndex,9,{35,43})
DRV_DEF_SDK_F(PeMemBlk,1,XlateOtagKey,reserved0,8,{27,34})
DRV_DEF_SDK_F(PeMemBlk,1,XlateOtagKey,otag,16,{11,26})
DRV_DEF_SDK_F(PeMemBlk,1,XlateOtagKey,sport,6,{5,10})
DRV_DEF_SDK_F(PeMemBlk,1,XlateOtagKey,keyType,4,{1,4})
DRV_DEF_SDK_F(PeMemBlk,1,XlateOtagKey,valid,1,{0,0})

DRV_DEF_SDK_D(PeMemBlk,1,XlateItagKey,0x0010,OP_INDIRECT,TBL_HASH,256,2,0x00254000)
DRV_DEF_SDK_F(PeMemBlk,1,XlateItagKey,ivmIndex,9,{35,43})
DRV_DEF_SDK_F(PeMemBlk,1,XlateItagKey,reserved0,8,{27,34})
DRV_DEF_SDK_F(PeMemBlk,1,XlateItagKey,itag,16,{11,26})
DRV_DEF_SDK_F(PeMemBlk,1,XlateItagKey,sport,6,{5,10})
DRV_DEF_SDK_F(PeMemBlk,1,XlateItagKey,keyType,4,{1,4})
DRV_DEF_SDK_F(PeMemBlk,1,XlateItagKey,valid,1,{0,0})

DRV_DEF_SDK_D(PeMemBlk,1,VlanHashView9,0x0010,OP_INDIRECT,TBL_HASH,256,3,0x00254000)
DRV_DEF_SDK_F(PeMemBlk,1,VlanHashView9,ivmIndex,9,{79,87})
DRV_DEF_SDK_F(PeMemBlk,1,VlanHashView9,reserved0,41,{38,78})
DRV_DEF_SDK_F(PeMemBlk,1,VlanHashView9,sip,32,{6,37})
DRV_DEF_SDK_F(PeMemBlk,1,VlanHashView9,keyType,4,{2,5})
DRV_DEF_SDK_F(PeMemBlk,1,VlanHashView9,valid,2,{0,1})

DRV_DEF_SDK_D(PeMemBlk,1,XlateMacKey0,0x0010,OP_INDIRECT,TBL_HASH,256,6,0x00254000)
DRV_DEF_SDK_F(PeMemBlk,1,XlateMacKey0,ivmIndex,9,{167,175})
DRV_DEF_SDK_F(PeMemBlk,1,XlateMacKey0,reserved0,25,{142,166})
DRV_DEF_SDK_F(PeMemBlk,1,XlateMacKey0,sip,128,{14,141})
DRV_DEF_SDK_F(PeMemBlk,1,XlateMacKey0,sport,6,{8,13})
DRV_DEF_SDK_F(PeMemBlk,1,XlateMacKey0,keyType,4,{4,7})
DRV_DEF_SDK_F(PeMemBlk,1,XlateMacKey0,valid,4,{0,3})

DRV_DEF_SDK_D(PeMemBlk,1,EvtTable,0x0010,OP_DIRECT,TBL_SRAM,4096,3,0x002e0000)
DRV_DEF_SDK_F(PeMemBlk,1,EvtTable,valid,1,{74,74})
DRV_DEF_SDK_F(PeMemBlk,1,EvtTable,epep2ndHash,3,{71,73})
DRV_DEF_SDK_F(PeMemBlk,1,EvtTable,eepp2ndHash,3,{68,70})
DRV_DEF_SDK_F(PeMemBlk,1,EvtTable,priSel,1,{67,67})
DRV_DEF_SDK_F(PeMemBlk,1,EvtTable,qosMode,1,{66,66})
DRV_DEF_SDK_F(PeMemBlk,1,EvtTable,vlanUntagMap,29,{37,65})
DRV_DEF_SDK_F(PeMemBlk,1,EvtTable,egressMstpIndex,5,{32,36})
DRV_DEF_SDK_F(PeMemBlk,1,EvtTable,stpidIndex,2,{30,31})
DRV_DEF_SDK_F(PeMemBlk,1,EvtTable,ctpidIndex,1,{29,29})
DRV_DEF_SDK_F(PeMemBlk,1,EvtTable,vlanMember,29,{0,28})

DRV_DEF_SDK_D(PeMemBlk,1,AclBaseAction,0x0010,OP_DIRECT,TBL_SRAM,128,4,0x00290000)
DRV_DEF_SDK_F(PeMemBlk,1,AclBaseAction,cpuFlowid,3,{98,100})
DRV_DEF_SDK_F(PeMemBlk,1,AclBaseAction,bypassLoopback,1,{97,97})
DRV_DEF_SDK_F(PeMemBlk,1,AclBaseAction,notModify,1,{96,96})
DRV_DEF_SDK_F(PeMemBlk,1,AclBaseAction,nniMaster,1,{95,95})
DRV_DEF_SDK_F(PeMemBlk,1,AclBaseAction,protectionWorkingPath,1,{94,94})
DRV_DEF_SDK_F(PeMemBlk,1,AclBaseAction,dropProtectPktEn,1,{93,93})
DRV_DEF_SDK_F(PeMemBlk,1,AclBaseAction,protectMode,3,{90,92})
DRV_DEF_SDK_F(PeMemBlk,1,AclBaseAction,bypassProtect,1,{89,89})
DRV_DEF_SDK_F(PeMemBlk,1,AclBaseAction,bypassLearning,1,{88,88})
DRV_DEF_SDK_F(PeMemBlk,1,AclBaseAction,bypassSpmac,1,{87,87})
DRV_DEF_SDK_F(PeMemBlk,1,AclBaseAction,bypassEvtCheck,1,{86,86})
DRV_DEF_SDK_F(PeMemBlk,1,AclBaseAction,bypassIvtCheck,1,{85,85})
DRV_DEF_SDK_F(PeMemBlk,1,AclBaseAction,bypassEgressStpState,1,{84,84})
DRV_DEF_SDK_F(PeMemBlk,1,AclBaseAction,bypassIngressStpState,1,{83,83})
DRV_DEF_SDK_F(PeMemBlk,1,AclBaseAction,bypassEvcDrop,1,{82,82})
DRV_DEF_SDK_F(PeMemBlk,1,AclBaseAction,bypassEapDrop,1,{81,81})
DRV_DEF_SDK_F(PeMemBlk,1,AclBaseAction,mirrorEn,2,{79,80})
DRV_DEF_SDK_F(PeMemBlk,1,AclBaseAction,egmirrorPortSel,6,{73,78})
DRV_DEF_SDK_F(PeMemBlk,1,AclBaseAction,copyToCpu,1,{72,72})
DRV_DEF_SDK_F(PeMemBlk,1,AclBaseAction,drop,1,{71,71})
DRV_DEF_SDK_F(PeMemBlk,1,AclBaseAction,loopbackEnable,1,{70,70})
DRV_DEF_SDK_F(PeMemBlk,1,AclBaseAction,loopbackIndex,5,{65,69})
DRV_DEF_SDK_F(PeMemBlk,1,AclBaseAction,redirectEnable,1,{64,64})
DRV_DEF_SDK_F(PeMemBlk,1,AclBaseAction,redirectPortBitmap,29,{35,63})
DRV_DEF_SDK_F(PeMemBlk,1,AclBaseAction,redirectLagBitmap,5,{30,34})
DRV_DEF_SDK_F(PeMemBlk,1,AclBaseAction,bitmapMode,1,{29,29})
DRV_DEF_SDK_F(PeMemBlk,1,AclBaseAction,expEgressPortBitmap,29,{0,28})

DRV_DEF_SDK_D(PeMemBlk,1,AclQosAction,0x0008,OP_DIRECT,TBL_SRAM,128,2,0x00294000)
DRV_DEF_SDK_F(PeMemBlk,1,AclQosAction,counterIndex,10,{41,50})
DRV_DEF_SDK_F(PeMemBlk,1,AclQosAction,counterEnable,1,{40,40})
DRV_DEF_SDK_F(PeMemBlk,1,AclQosAction,policeMode,1,{39,39})
DRV_DEF_SDK_F(PeMemBlk,1,AclQosAction,policeIndex,6,{33,38})
DRV_DEF_SDK_F(PeMemBlk,1,AclQosAction,policePosition,1,{32,32})
DRV_DEF_SDK_F(PeMemBlk,1,AclQosAction,policeExpDport,5,{27,31})
DRV_DEF_SDK_F(PeMemBlk,1,AclQosAction,qp2cpu,6,{21,26})
DRV_DEF_SDK_F(PeMemBlk,1,AclQosAction,changeQp2cpu,1,{20,20})
DRV_DEF_SDK_F(PeMemBlk,1,AclQosAction,remarkScosMode,2,{18,19})
DRV_DEF_SDK_F(PeMemBlk,1,AclQosAction,remarkDscpMode,2,{16,17})
DRV_DEF_SDK_F(PeMemBlk,1,AclQosAction,remarkScos,4,{12,15})
DRV_DEF_SDK_F(PeMemBlk,1,AclQosAction,remarkDscp,6,{6,11})
DRV_DEF_SDK_F(PeMemBlk,1,AclQosAction,trustPriMode,2,{4,5})
DRV_DEF_SDK_F(PeMemBlk,1,AclQosAction,priIndex,4,{0,3})

DRV_DEF_M(PeRegBlk,1) // 00200000
DRV_DEF_SDK_D(PeRegBlk,1,PeCpuAccessReq,0x0010,OP_DIRECT,TBL_SRAM,1,1,0x00290c00)
DRV_DEF_SDK_F(PeRegBlk,1,PeCpuAccessReq,req,1,{31,31})
DRV_DEF_SDK_F(PeRegBlk,1,PeCpuAccessReq,reqType,1,{30,30})
DRV_DEF_SDK_F(PeRegBlk,1,PeCpuAccessReq,page,6,{24,29})
DRV_DEF_SDK_F(PeRegBlk,1,PeCpuAccessReq,addr,24,{0,23})

DRV_DEF_SDK_D(PeRegBlk,1,PeCpuAccessWdata,0x0020,OP_DIRECT,TBL_SRAM,1,8,0x00290c40)
DRV_DEF_SDK_F(PeRegBlk,1,PeCpuAccessWdata,data,256,{0,255})

DRV_DEF_SDK_D(PeRegBlk,1,PeCpuAccessRdata,0x0040,OP_DIRECT,TBL_SRAM,1,9,0x00290c80)
DRV_DEF_SDK_F(PeRegBlk,1,PeCpuAccessRdata,complete,1,{256,256})
DRV_DEF_SDK_F(PeRegBlk,1,PeCpuAccessRdata,data,256,{0,255})

DRV_DEF_SDK_D(PeRegBlk,1,PeCpuAccessHashReq,0x0010,OP_DIRECT,TBL_SRAM,1,1,0x00290c08)
DRV_DEF_SDK_F(PeRegBlk,1,PeCpuAccessHashReq,searchStart,1,{23,23})
DRV_DEF_SDK_F(PeRegBlk,1,PeCpuAccessHashReq,searchType,3,{20,22})
DRV_DEF_SDK_F(PeRegBlk,1,PeCpuAccessHashReq,keyType,4,{16,19})
DRV_DEF_SDK_F(PeRegBlk,1,PeCpuAccessHashReq,directAddr,16,{0,15})

DRV_DEF_SDK_D(PeRegBlk,1,PeCpuAccessHashStatus,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x00290c10)
DRV_DEF_SDK_F(PeRegBlk,1,PeCpuAccessHashStatus,keyType,4,{3,6})
DRV_DEF_SDK_F(PeRegBlk,1,PeCpuAccessHashStatus,learned,1,{2,2})
DRV_DEF_SDK_F(PeRegBlk,1,PeCpuAccessHashStatus,hitMiss,1,{1,1})
DRV_DEF_SDK_F(PeRegBlk,1,PeCpuAccessHashStatus,searchDone,1,{0,0})

DRV_DEF_SDK_D(PeRegBlk,1,PeCpuAccessHashAddr,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x00290c18)
DRV_DEF_SDK_F(PeRegBlk,1,PeCpuAccessHashAddr,tablePtr,16,{0,15})

DRV_DEF_SDK_D(PeRegBlk,1,PeCpuAccessHashWdata,0x0020,OP_DIRECT,TBL_SRAM,1,8,0x00290d00)
DRV_DEF_SDK_F(PeRegBlk,1,PeCpuAccessHashWdata,data,256,{0,255})

DRV_DEF_SDK_D(PeRegBlk,1,PeCpuAccessHashRdata,0x0020,OP_DIRECT,TBL_SRAM,1,8,0x00290d40)
DRV_DEF_SDK_F(PeRegBlk,1,PeCpuAccessHashRdata,data,256,{0,255})

DRV_DEF_SDK_D(PeRegBlk,1,GlobalCtrl,0x0010,OP_DIRECT,TBL_SRAM,1,2,0x00200460)
DRV_DEF_SDK_F(PeRegBlk,1,GlobalCtrl,cntRcEn,1,{45,45})
DRV_DEF_SDK_F(PeRegBlk,1,GlobalCtrl,ilpDropedByOam,1,{44,44})
DRV_DEF_SDK_F(PeRegBlk,1,GlobalCtrl,egmirrorPortSel,6,{38,43})
DRV_DEF_SDK_F(PeRegBlk,1,GlobalCtrl,mirrorDport,6,{32,37})
DRV_DEF_SDK_F(PeRegBlk,1,GlobalCtrl,reserved0,5,{27,31})
DRV_DEF_SDK_F(PeRegBlk,1,GlobalCtrl,protectIxg4Subport,3,{24,26})
DRV_DEF_SDK_F(PeRegBlk,1,GlobalCtrl,protectIxg3Subport,3,{21,23})
DRV_DEF_SDK_F(PeRegBlk,1,GlobalCtrl,udfOffsetL4,3,{18,20})
DRV_DEF_SDK_F(PeRegBlk,1,GlobalCtrl,udfOffsetIpv6,3,{15,17})
DRV_DEF_SDK_F(PeRegBlk,1,GlobalCtrl,udfOffsetIpv4,3,{12,14})
DRV_DEF_SDK_F(PeRegBlk,1,GlobalCtrl,udfOffsetL2,3,{9,11})
DRV_DEF_SDK_F(PeRegBlk,1,GlobalCtrl,nniTxProtectionSwitch,2,{7,8})
DRV_DEF_SDK_F(PeRegBlk,1,GlobalCtrl,nniRxProtectionSwitch,2,{5,6})
DRV_DEF_SDK_F(PeRegBlk,1,GlobalCtrl,vlanChkFailTocpu,1,{4,4})
DRV_DEF_SDK_F(PeRegBlk,1,GlobalCtrl,vlanUnknownTocpu,1,{3,3})
DRV_DEF_SDK_F(PeRegBlk,1,GlobalCtrl,receiveBpduTocpu,1,{2,2})
DRV_DEF_SDK_F(PeRegBlk,1,GlobalCtrl,pkt1588QosEnable,1,{1,1})
DRV_DEF_SDK_F(PeRegBlk,1,GlobalCtrl,pkt1588MeterEnable,1,{0,0})

DRV_DEF_D(PeRegBlk,1,ToCpuAction,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x00200470)
DRV_DEF_F(PeRegBlk,1,ToCpuAction,notModify,32,{0,31})

DRV_DEF_SDK_D(PeRegBlk,1,TocpuQp,0x0004,OP_DIRECT,TBL_SRAM,32,1,0x00200500)
DRV_DEF_SDK_F(PeRegBlk,1,TocpuQp,useReason2qp,1,{6,6})
DRV_DEF_SDK_F(PeRegBlk,1,TocpuQp,qp,6,{0,5})

DRV_DEF_SDK_D(PeRegBlk,1,IngressPort,0x0020,OP_DIRECT,TBL_SRAM,29,7,0x00200000)
DRV_DEF_SDK_F(PeRegBlk,1,IngressPort,trunkId,3,{214,216})
DRV_DEF_SDK_F(PeRegBlk,1,IngressPort,trunkVld,1,{213,213})
DRV_DEF_SDK_F(PeRegBlk,1,IngressPort,spmacGroupid,4,{209,212})
DRV_DEF_SDK_F(PeRegBlk,1,IngressPort,ivmGroupid,3,{206,208})
DRV_DEF_SDK_F(PeRegBlk,1,IngressPort,qosProcMode,1,{205,205})
DRV_DEF_SDK_F(PeRegBlk,1,IngressPort,counterEnable,1,{204,204})
DRV_DEF_SDK_F(PeRegBlk,1,IngressPort,counterIndex,10,{194,203})
DRV_DEF_SDK_F(PeRegBlk,1,IngressPort,remarkDscpMode,2,{192,193})
DRV_DEF_SDK_F(PeRegBlk,1,IngressPort,remarkDscp,6,{186,191})
DRV_DEF_SDK_F(PeRegBlk,1,IngressPort,remarkScosMode,2,{184,185})
DRV_DEF_SDK_F(PeRegBlk,1,IngressPort,remarkScos,4,{180,183})
DRV_DEF_SDK_F(PeRegBlk,1,IngressPort,remarkCcos,4,{176,179})
DRV_DEF_SDK_F(PeRegBlk,1,IngressPort,priIndex,4,{172,175})
DRV_DEF_SDK_F(PeRegBlk,1,IngressPort,trustPriMode,2,{170,171})
DRV_DEF_SDK_F(PeRegBlk,1,IngressPort,policeIndex,6,{164,169})
DRV_DEF_SDK_F(PeRegBlk,1,IngressPort,policeMode,1,{163,163})
DRV_DEF_SDK_F(PeRegBlk,1,IngressPort,localPri,4,{159,162})
DRV_DEF_SDK_F(PeRegBlk,1,IngressPort,localColor,2,{157,158})
DRV_DEF_SDK_F(PeRegBlk,1,IngressPort,useCvidAsOvid,1,{156,156})
DRV_DEF_SDK_F(PeRegBlk,1,IngressPort,trustVid,1,{155,155})
DRV_DEF_SDK_F(PeRegBlk,1,IngressPort,bcMask,29,{126,154})
DRV_DEF_SDK_F(PeRegBlk,1,IngressPort,mlfMask,29,{97,125})
DRV_DEF_SDK_F(PeRegBlk,1,IngressPort,ulfMask,29,{68,96})
DRV_DEF_SDK_F(PeRegBlk,1,IngressPort,egressPortMask,29,{39,67})
DRV_DEF_SDK_F(PeRegBlk,1,IngressPort,eapBlock,1,{38,38})
DRV_DEF_SDK_F(PeRegBlk,1,IngressPort,stpState,3,{35,37})
DRV_DEF_SDK_F(PeRegBlk,1,IngressPort,ethoamEnable,1,{34,34})
DRV_DEF_SDK_F(PeRegBlk,1,IngressPort,ipv6OptionTocpu,1,{33,33})
DRV_DEF_SDK_F(PeRegBlk,1,IngressPort,ipv4OptionTocpu,1,{32,32})
DRV_DEF_SDK_F(PeRegBlk,1,IngressPort,ieee1588v2Enable,1,{31,31})
DRV_DEF_SDK_F(PeRegBlk,1,IngressPort,ingress1pMapEna,1,{30,30})
DRV_DEF_SDK_F(PeRegBlk,1,IngressPort,mirrorEn,1,{29,29})
DRV_DEF_SDK_F(PeRegBlk,1,IngressPort,stpidEnable,4,{25,28})
DRV_DEF_SDK_F(PeRegBlk,1,IngressPort,ctpidEnable,2,{23,24})
DRV_DEF_SDK_F(PeRegBlk,1,IngressPort,afterctagtpidEnable,2,{21,22})
DRV_DEF_SDK_F(PeRegBlk,1,IngressPort,vlanTpidVerifyEnable,1,{20,20})
DRV_DEF_SDK_F(PeRegBlk,1,IngressPort,no1pPkt,1,{19,19})
DRV_DEF_SDK_F(PeRegBlk,1,IngressPort,noTagPkt,1,{18,18})
DRV_DEF_SDK_F(PeRegBlk,1,IngressPort,noUntagPkt,1,{17,17})
DRV_DEF_SDK_F(PeRegBlk,1,IngressPort,bypassStp,1,{16,16})
DRV_DEF_SDK_F(PeRegBlk,1,IngressPort,bypassVlanCheck,1,{15,15})
DRV_DEF_SDK_F(PeRegBlk,1,IngressPort,pvid,12,{3,14})
DRV_DEF_SDK_F(PeRegBlk,1,IngressPort,ivmXEn,1,{2,2})
DRV_DEF_SDK_F(PeRegBlk,1,IngressPort,ivmMode,2,{0,1})

DRV_DEF_SDK_D(PeRegBlk,1,Stagtpid,0x0008,OP_DIRECT,TBL_SRAM,1,2,0x00200400)
DRV_DEF_SDK_F(PeRegBlk,1,Stagtpid,tpid3,16,{48,63})
DRV_DEF_SDK_F(PeRegBlk,1,Stagtpid,tpid2,16,{32,47})
DRV_DEF_SDK_F(PeRegBlk,1,Stagtpid,tpid1,16,{16,31})
DRV_DEF_SDK_F(PeRegBlk,1,Stagtpid,tpid0,16,{0,15})

DRV_DEF_SDK_D(PeRegBlk,1,Ctagtpid,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x00200410)
DRV_DEF_SDK_F(PeRegBlk,1,Ctagtpid,tpid1,16,{16,31})
DRV_DEF_SDK_F(PeRegBlk,1,Ctagtpid,tpid0,16,{0,15})

DRV_DEF_D(PeRegBlk,1,Afterctagtpid,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x00200420)
DRV_DEF_F(PeRegBlk,1,Afterctagtpid,tpid1,16,{16,31})
DRV_DEF_F(PeRegBlk,1,Afterctagtpid,tpid0,16,{0,15})

DRV_DEF_SDK_D(PeRegBlk,1,Ptagtpid,0x0008,OP_DIRECT,TBL_SRAM,1,1,0x00200430)
DRV_DEF_SDK_F(PeRegBlk,1,Ptagtpid,tpidCpu,16,{16,31})
DRV_DEF_SDK_F(PeRegBlk,1,Ptagtpid,tpidOam,16,{0,15})

DRV_DEF_SDK_D(PeRegBlk,1,LagHashControl,0x0004,OP_DIRECT,TBL_SRAM,5,1,0x00200440)
DRV_DEF_SDK_F(PeRegBlk,1,LagHashControl,keySel,10,{0,9})

DRV_DEF_SDK_D(PeRegBlk,1,HostMac,0x0010,OP_DIRECT,TBL_SRAM,1,2,0x00200480)
DRV_DEF_SDK_F(PeRegBlk,1,HostMac,mac,48,{0,47})

DRV_DEF_SDK_D(PeRegBlk,1,SpmacUcMac,0x0010,OP_DIRECT,TBL_SRAM,1,2,0x00200490)
DRV_DEF_SDK_F(PeRegBlk,1,SpmacUcMac,mac,48,{0,47})

DRV_DEF_D(PeRegBlk,1,HostIpv6,0x0010,OP_DIRECT,TBL_SRAM,1,4,0x002004c0)
DRV_DEF_F(PeRegBlk,1,HostIpv6,ip,128,{0,127})

DRV_DEF_D(PeRegBlk,1,HostIpv4,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x002004e0)
DRV_DEF_F(PeRegBlk,1,HostIpv4,ip,32,{0,31})

DRV_DEF_D(PeRegBlk,1,TtlCfg,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x002004f0)
DRV_DEF_F(PeRegBlk,1,TtlCfg,ttl,8,{0,7})

DRV_DEF_SDK_D(PeRegBlk,1,EgressPort,0x0008,OP_DIRECT,TBL_SRAM,29,2,0x00291800)
DRV_DEF_SDK_F(PeRegBlk,1,EgressPort,evmGroupid,3,{40,42})
DRV_DEF_SDK_F(PeRegBlk,1,EgressPort,evmMode,2,{38,39})
DRV_DEF_SDK_F(PeRegBlk,1,EgressPort,portDown,1,{37,37})
DRV_DEF_SDK_F(PeRegBlk,1,EgressPort,stpBlock,1,{36,36})
DRV_DEF_SDK_F(PeRegBlk,1,EgressPort,eapBlock,1,{35,35})
DRV_DEF_SDK_F(PeRegBlk,1,EgressPort,mirrorEn,1,{34,34})
DRV_DEF_SDK_F(PeRegBlk,1,EgressPort,blockBcFlooding,1,{33,33})
DRV_DEF_SDK_F(PeRegBlk,1,EgressPort,blockMlfFlooding,1,{32,32})
DRV_DEF_SDK_F(PeRegBlk,1,EgressPort,blockUlfFlooding,1,{31,31})
DRV_DEF_SDK_F(PeRegBlk,1,EgressPort,bypassStp,1,{30,30})
DRV_DEF_SDK_F(PeRegBlk,1,EgressPort,bypassVlanCheck,1,{29,29})
DRV_DEF_SDK_F(PeRegBlk,1,EgressPort,priIndex,4,{25,28})
DRV_DEF_SDK_F(PeRegBlk,1,EgressPort,qosProcMode,1,{24,24})
DRV_DEF_SDK_F(PeRegBlk,1,EgressPort,remarkScos,4,{20,23})
DRV_DEF_SDK_F(PeRegBlk,1,EgressPort,remarkScosMode,2,{18,19})
DRV_DEF_SDK_F(PeRegBlk,1,EgressPort,remarkCcosMode,2,{16,17})
DRV_DEF_SDK_F(PeRegBlk,1,EgressPort,remarkCcos,4,{12,15})
DRV_DEF_SDK_F(PeRegBlk,1,EgressPort,remarkDscpMode,2,{10,11})
DRV_DEF_SDK_F(PeRegBlk,1,EgressPort,remarkDscp,6,{4,9})
DRV_DEF_SDK_F(PeRegBlk,1,EgressPort,portTpidEnable,1,{3,3})
DRV_DEF_SDK_F(PeRegBlk,1,EgressPort,stpidIndex,2,{1,2})
DRV_DEF_SDK_F(PeRegBlk,1,EgressPort,ctpidIndex,1,{0,0})

DRV_DEF_SDK_D(PeRegBlk,1,ChecksumDebug,0x0010,OP_DIRECT,TBL_SRAM,1,1,0x0031f800)
DRV_DEF_SDK_F(PeRegBlk,1,ChecksumDebug,ipv6IcmpChksumRecalcEn,1,{20,20})
DRV_DEF_SDK_F(PeRegBlk,1,ChecksumDebug,ipv6UdpChksumRecalcEn,1,{19,19})
DRV_DEF_SDK_F(PeRegBlk,1,ChecksumDebug,ipv6TcpChksumRecalcEn,1,{18,18})
DRV_DEF_SDK_F(PeRegBlk,1,ChecksumDebug,ipv4IcmpChksumRecalcEn,1,{17,17})
DRV_DEF_SDK_F(PeRegBlk,1,ChecksumDebug,ipv4UdpChksumRecalcEn,1,{16,16})
DRV_DEF_SDK_F(PeRegBlk,1,ChecksumDebug,ipv4TcpChksumRecalcEn,1,{15,15})
DRV_DEF_SDK_F(PeRegBlk,1,ChecksumDebug,ipv4ChksumRecalcEn,1,{14,14})
DRV_DEF_SDK_F(PeRegBlk,1,ChecksumDebug,ipv6IcmpChksumCtrl,2,{12,13})
DRV_DEF_SDK_F(PeRegBlk,1,ChecksumDebug,ipv6UdpChksumCtrl,2,{10,11})
DRV_DEF_SDK_F(PeRegBlk,1,ChecksumDebug,ipv6TcpChksumCtrl,2,{8,9})
DRV_DEF_SDK_F(PeRegBlk,1,ChecksumDebug,ipv4IcmpChksumCtrl,2,{6,7})
DRV_DEF_SDK_F(PeRegBlk,1,ChecksumDebug,ipv4UdpChksumCtrl,2,{4,5})
DRV_DEF_SDK_F(PeRegBlk,1,ChecksumDebug,ipv4TcpChksumCtrl,2,{2,3})
DRV_DEF_SDK_F(PeRegBlk,1,ChecksumDebug,ipv4ChksumCtrl,2,{0,1})

DRV_DEF_D(PeRegBlk,1,IngressDebugCnt,0x0010,OP_DIRECT,TBL_SRAM,36,4,0x00323000)
DRV_DEF_F(PeRegBlk,1,IngressDebugCnt,dsetPort,16,{112,127})
DRV_DEF_F(PeRegBlk,1,IngressDebugCnt,pktEop,16,{96,111})
DRV_DEF_F(PeRegBlk,1,IngressDebugCnt,pktSop,16,{80,95})
DRV_DEF_F(PeRegBlk,1,IngressDebugCnt,resolOut,16,{64,79})
DRV_DEF_F(PeRegBlk,1,IngressDebugCnt,parserOut,16,{48,63})
DRV_DEF_F(PeRegBlk,1,IngressDebugCnt,ivmIn,16,{32,47})
DRV_DEF_F(PeRegBlk,1,IngressDebugCnt,parserInEop,16,{16,31})
DRV_DEF_F(PeRegBlk,1,IngressDebugCnt,parserInSop,16,{0,15})

DRV_DEF_D(PeRegBlk,1,EgressDebugCnt,0x0010,OP_DIRECT,TBL_SRAM,29,2,0x00323400)
DRV_DEF_F(PeRegBlk,1,EgressDebugCnt,editOut,16,{48,63})
DRV_DEF_F(PeRegBlk,1,EgressDebugCnt,pktEop,16,{32,47})
DRV_DEF_F(PeRegBlk,1,EgressDebugCnt,pktSop,16,{16,31})
DRV_DEF_F(PeRegBlk,1,EgressDebugCnt,parserIn,16,{0,15})

DRV_DEF_D(PeRegBlk,1,DebugCntClr,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x00323800)
DRV_DEF_F(PeRegBlk,1,DebugCntClr,egressClr,1,{1,1})
DRV_DEF_F(PeRegBlk,1,DebugCntClr,ingressClr,1,{0,0})

DRV_DEF_D(PeRegBlk,1,DebugReg,0x0004,OP_DIRECT,TBL_SRAM,32,1,0x00324000)
DRV_DEF_F(PeRegBlk,1,DebugReg,debug,32,{0,31})

DRV_DEF_D(PeRegBlk,1,DebugCtrl,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x00325000)
DRV_DEF_F(PeRegBlk,1,DebugCtrl,en,1,{8,8})
DRV_DEF_F(PeRegBlk,1,DebugCtrl,index,8,{0,7})

DRV_DEF_SDK_D(PeRegBlk,1,SecurityFilterRule,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x00290b80)
DRV_DEF_SDK_F(PeRegBlk,1,SecurityFilterRule,icmpv6Fragment,1,{14,14})
DRV_DEF_SDK_F(PeRegBlk,1,SecurityFilterRule,icmpv6Longping,1,{13,13})
DRV_DEF_SDK_F(PeRegBlk,1,SecurityFilterRule,icmpv4Longping,1,{12,12})
DRV_DEF_SDK_F(PeRegBlk,1,SecurityFilterRule,ipFragErr,1,{11,11})
DRV_DEF_SDK_F(PeRegBlk,1,SecurityFilterRule,icmpv4Fragment,1,{10,10})
DRV_DEF_SDK_F(PeRegBlk,1,SecurityFilterRule,tcpFragerror,1,{9,9})
DRV_DEF_SDK_F(PeRegBlk,1,SecurityFilterRule,tinyTcp,1,{8,8})
DRV_DEF_SDK_F(PeRegBlk,1,SecurityFilterRule,tcpSynerror,1,{7,7})
DRV_DEF_SDK_F(PeRegBlk,1,SecurityFilterRule,tcpSynfinscan,1,{6,6})
DRV_DEF_SDK_F(PeRegBlk,1,SecurityFilterRule,tcpXmasscan,1,{5,5})
DRV_DEF_SDK_F(PeRegBlk,1,SecurityFilterRule,tcpNullscan,1,{4,4})
DRV_DEF_SDK_F(PeRegBlk,1,SecurityFilterRule,udpBlat,1,{3,3})
DRV_DEF_SDK_F(PeRegBlk,1,SecurityFilterRule,tcpBlat,1,{2,2})
DRV_DEF_SDK_F(PeRegBlk,1,SecurityFilterRule,ipLand,1,{1,1})
DRV_DEF_SDK_F(PeRegBlk,1,SecurityFilterRule,macLand,1,{0,0})

DRV_DEF_D(PeRegBlk,1,DosSize,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x00290bc0)
DRV_DEF_F(PeRegBlk,1,DosSize,maxIcmpv6Size,11,{11,21})
DRV_DEF_F(PeRegBlk,1,DosSize,maxIcmpv4Size,11,{0,10})

DRV_DEF_SDK_D(PeRegBlk,1,PmacKey,0x0020,OP_DIRECT,TBL_SRAM,16,5,0x00200c00)
DRV_DEF_SDK_F(PeRegBlk,1,PmacKey,valid,1,{140,140})
DRV_DEF_SDK_F(PeRegBlk,1,PmacKey,maskOfSourcePort,1,{139,139})
DRV_DEF_SDK_F(PeRegBlk,1,PmacKey,maskOfDestinationPort,1,{138,138})
DRV_DEF_SDK_F(PeRegBlk,1,PmacKey,maskOfIpProtocol,1,{137,137})
DRV_DEF_SDK_F(PeRegBlk,1,PmacKey,maskOfSubtype,1,{136,136})
DRV_DEF_SDK_F(PeRegBlk,1,PmacKey,maskOfOpcode,1,{135,135})
DRV_DEF_SDK_F(PeRegBlk,1,PmacKey,maskL4Status,1,{134,134})
DRV_DEF_SDK_F(PeRegBlk,1,PmacKey,maskIpFrag,1,{133,133})
DRV_DEF_SDK_F(PeRegBlk,1,PmacKey,maskOfIpStatus,1,{132,132})
DRV_DEF_SDK_F(PeRegBlk,1,PmacKey,maskOfFramingType,1,{131,131})
DRV_DEF_SDK_F(PeRegBlk,1,PmacKey,maskOfEthertype,1,{130,130})
DRV_DEF_SDK_F(PeRegBlk,1,PmacKey,maskOfDa,1,{129,129})
DRV_DEF_SDK_F(PeRegBlk,1,PmacKey,sourcePortNumber,16,{113,128})
DRV_DEF_SDK_F(PeRegBlk,1,PmacKey,destinationPortNumber,16,{97,112})
DRV_DEF_SDK_F(PeRegBlk,1,PmacKey,ipProtocol,8,{89,96})
DRV_DEF_SDK_F(PeRegBlk,1,PmacKey,subtype,8,{81,88})
DRV_DEF_SDK_F(PeRegBlk,1,PmacKey,opcode,8,{73,80})
DRV_DEF_SDK_F(PeRegBlk,1,PmacKey,l4Status,2,{71,72})
DRV_DEF_SDK_F(PeRegBlk,1,PmacKey,ipFrag,3,{68,70})
DRV_DEF_SDK_F(PeRegBlk,1,PmacKey,ipStatus,2,{66,67})
DRV_DEF_SDK_F(PeRegBlk,1,PmacKey,framingType,2,{64,65})
DRV_DEF_SDK_F(PeRegBlk,1,PmacKey,eType,16,{48,63})
DRV_DEF_SDK_F(PeRegBlk,1,PmacKey,da,48,{0,47})

DRV_DEF_SDK_D(PeRegBlk,1,Port2vlan,0x0004,OP_DIRECT,TBL_SRAM,29,1,0x0020a800)
DRV_DEF_SDK_F(PeRegBlk,1,Port2vlan,ivmIndex,12,{0,11})

DRV_DEF_SDK_D(PeRegBlk,1,IvmXReg,0x0010,OP_DIRECT,TBL_SRAM_MASK,16,4,0x0020a900)
DRV_DEF_SDK_F(PeRegBlk,1,IvmXReg,valid,1,{100,100})
DRV_DEF_SDK_F(PeRegBlk,1,IvmXReg,cvid,12,{88,99})
DRV_DEF_SDK_F(PeRegBlk,1,IvmXReg,svid,12,{76,87})
DRV_DEF_SDK_F(PeRegBlk,1,IvmXReg,framingType,2,{74,75})
DRV_DEF_SDK_F(PeRegBlk,1,IvmXReg,ctagStatus,2,{72,73})
DRV_DEF_SDK_F(PeRegBlk,1,IvmXReg,stagStatus,2,{70,71})
DRV_DEF_SDK_F(PeRegBlk,1,IvmXReg,etherType,16,{54,69})
DRV_DEF_SDK_F(PeRegBlk,1,IvmXReg,sa,48,{6,53})
DRV_DEF_SDK_F(PeRegBlk,1,IvmXReg,sport,6,{0,5})

DRV_DEF_SDK_D(PeRegBlk,1,IvmXMaskReg,0x0008,OP_DIRECT,TBL_SRAM_MASK,16,2,0x0020ad00)
DRV_DEF_SDK_F(PeRegBlk,1,IvmXMaskReg,cvidMask,12,{23,34})
DRV_DEF_SDK_F(PeRegBlk,1,IvmXMaskReg,svidMask,12,{11,22})
DRV_DEF_SDK_F(PeRegBlk,1,IvmXMaskReg,framingTypeMask,1,{10,10})
DRV_DEF_SDK_F(PeRegBlk,1,IvmXMaskReg,ctagStatusMask,1,{9,9})
DRV_DEF_SDK_F(PeRegBlk,1,IvmXMaskReg,stagStatusMask,1,{8,8})
DRV_DEF_SDK_F(PeRegBlk,1,IvmXMaskReg,etherTypeMask,1,{7,7})
DRV_DEF_SDK_F(PeRegBlk,1,IvmXMaskReg,saMask,6,{1,6})
DRV_DEF_SDK_F(PeRegBlk,1,IvmXMaskReg,sportMask,1,{0,0})

DRV_DEF_SDK_D(PeRegBlk,1,VlanPortCtrl,0x0004,OP_DIRECT,TBL_SRAM,29,1,0x00250400)
DRV_DEF_SDK_F(PeRegBlk,1,VlanPortCtrl,keyType1,4,{9,12})
DRV_DEF_SDK_F(PeRegBlk,1,VlanPortCtrl,keyType2,4,{5,8})
DRV_DEF_SDK_F(PeRegBlk,1,VlanPortCtrl,rangeVidMode,2,{3,4})
DRV_DEF_SDK_F(PeRegBlk,1,VlanPortCtrl,vrangeIdx,2,{1,2})
DRV_DEF_SDK_F(PeRegBlk,1,VlanPortCtrl,vrangeEn,1,{0,0})

DRV_DEF_D(PeRegBlk,1,VlanHashCtrl,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x00250480)
DRV_DEF_F(PeRegBlk,1,VlanHashCtrl,hashSeed,8,{0,7})

DRV_DEF_SDK_D(PeRegBlk,1,VlanRange,0x0010,OP_DIRECT,TBL_SRAM,4,4,0x00250500)
DRV_DEF_SDK_F(PeRegBlk,1,VlanRange,vlan3Max,12,{108,119})
DRV_DEF_SDK_F(PeRegBlk,1,VlanRange,vlan3Min,12,{96,107})
DRV_DEF_SDK_F(PeRegBlk,1,VlanRange,reserved0,8,{88,95})
DRV_DEF_SDK_F(PeRegBlk,1,VlanRange,vlan2Max,12,{76,87})
DRV_DEF_SDK_F(PeRegBlk,1,VlanRange,vlan2Min,12,{64,75})
DRV_DEF_SDK_F(PeRegBlk,1,VlanRange,reserved1,8,{56,63})
DRV_DEF_SDK_F(PeRegBlk,1,VlanRange,vlan1Max,12,{44,55})
DRV_DEF_SDK_F(PeRegBlk,1,VlanRange,vlan1Min,12,{32,43})
DRV_DEF_SDK_F(PeRegBlk,1,VlanRange,reserved2,8,{24,31})
DRV_DEF_SDK_F(PeRegBlk,1,VlanRange,vlan0Max,12,{12,23})
DRV_DEF_SDK_F(PeRegBlk,1,VlanRange,vlan0Min,12,{0,11})

DRV_DEF_D(PeRegBlk,1,EvmMiss,0x0004,OP_DIRECT,TBL_SRAM,29,1,0x00291a00)
DRV_DEF_F(PeRegBlk,1,EvmMiss,evmUtMiss,1,{14,14})
DRV_DEF_F(PeRegBlk,1,EvmMiss,evmTMissDrop,1,{13,13})
DRV_DEF_F(PeRegBlk,1,EvmMiss,evmUtMissDrop,1,{12,12})
DRV_DEF_F(PeRegBlk,1,EvmMiss,evmIndex,12,{0,11})

DRV_DEF_SDK_D(PeRegBlk,1,UdfCam,0x0010,OP_DIRECT,TBL_SRAM_MASK,8,4,0x00250900)
DRV_DEF_SDK_F(PeRegBlk,1,UdfCam,l4Dport,16,{82,97})
DRV_DEF_SDK_F(PeRegBlk,1,UdfCam,l4Sport,16,{66,81})
DRV_DEF_SDK_F(PeRegBlk,1,UdfCam,l4Type,3,{63,65})
DRV_DEF_SDK_F(PeRegBlk,1,UdfCam,fragmentFlag,2,{61,62})
DRV_DEF_SDK_F(PeRegBlk,1,UdfCam,ipOption,1,{60,60})
DRV_DEF_SDK_F(PeRegBlk,1,UdfCam,ipProtocol,8,{52,59})
DRV_DEF_SDK_F(PeRegBlk,1,UdfCam,ethtype,16,{36,51})
DRV_DEF_SDK_F(PeRegBlk,1,UdfCam,l2Type,2,{34,35})
DRV_DEF_SDK_F(PeRegBlk,1,UdfCam,l2TagStatus,2,{32,33})
DRV_DEF_SDK_F(PeRegBlk,1,UdfCam,sportBitmap,29,{3,31})
DRV_DEF_SDK_F(PeRegBlk,1,UdfCam,portType,2,{1,2})
DRV_DEF_SDK_F(PeRegBlk,1,UdfCam,valid,1,{0,0})

DRV_DEF_D(PeRegBlk,1,UdfPortCtrl,0x0010,OP_DIRECT,TBL_SRAM,1,1,0x00250a80)
DRV_DEF_F(PeRegBlk,1,UdfPortCtrl,bitmapMode,29,{0,28})

DRV_DEF_SDK_D(PeRegBlk,1,UdfOffset,0x0008,OP_DIRECT,TBL_SRAM,8,1,0x00250a00)
DRV_DEF_SDK_F(PeRegBlk,1,UdfOffset,udf3Offset,5,{23,27})
DRV_DEF_SDK_F(PeRegBlk,1,UdfOffset,udf2Offset,5,{18,22})
DRV_DEF_SDK_F(PeRegBlk,1,UdfOffset,udf1Offset,5,{13,17})
DRV_DEF_SDK_F(PeRegBlk,1,UdfOffset,udf0Offset,5,{8,12})
DRV_DEF_SDK_F(PeRegBlk,1,UdfOffset,udf3BaseType,2,{6,7})
DRV_DEF_SDK_F(PeRegBlk,1,UdfOffset,udf2BaseType,2,{4,5})
DRV_DEF_SDK_F(PeRegBlk,1,UdfOffset,udf1BaseType,2,{2,3})
DRV_DEF_SDK_F(PeRegBlk,1,UdfOffset,udf0BaseType,2,{0,1})

DRV_DEF_SDK_D(PeRegBlk,1,AclGlobalKeyMode,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x00271400)
DRV_DEF_SDK_F(PeRegBlk,1,AclGlobalKeyMode,keyMode,2,{0,1})

DRV_DEF_SDK_D(PeRegBlk,1,AclGlobalKeyCtrl,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x00271440)
DRV_DEF_SDK_F(PeRegBlk,1,AclGlobalKeyCtrl,macSel,1,{14,14})
DRV_DEF_SDK_F(PeRegBlk,1,AclGlobalKeyCtrl,ipv6Sa32Sel,5,{9,13})
DRV_DEF_SDK_F(PeRegBlk,1,AclGlobalKeyCtrl,ipv6Da32Sel,5,{4,8})
DRV_DEF_SDK_F(PeRegBlk,1,AclGlobalKeyCtrl,ipv6Addr1Mode,1,{3,3})
DRV_DEF_SDK_F(PeRegBlk,1,AclGlobalKeyCtrl,ipv6Addr2Mode,1,{2,2})
DRV_DEF_SDK_F(PeRegBlk,1,AclGlobalKeyCtrl,vidMode,1,{1,1})
DRV_DEF_SDK_F(PeRegBlk,1,AclGlobalKeyCtrl,dscpMode,1,{0,0})

DRV_DEF_SDK_D(PeRegBlk,1,AclPortKeyConfig,0x0008,OP_DIRECT,TBL_SRAM,29,2,0x00271500)
DRV_DEF_SDK_F(PeRegBlk,1,AclPortKeyConfig,keyRangeEn,9,{37,45})
DRV_DEF_SDK_F(PeRegBlk,1,AclPortKeyConfig,key3UdfMode,1,{36,36})
DRV_DEF_SDK_F(PeRegBlk,1,AclPortKeyConfig,slice7KeyMode,4,{32,35})
DRV_DEF_SDK_F(PeRegBlk,1,AclPortKeyConfig,slice6KeyMode,4,{28,31})
DRV_DEF_SDK_F(PeRegBlk,1,AclPortKeyConfig,slice5KeyMode,4,{24,27})
DRV_DEF_SDK_F(PeRegBlk,1,AclPortKeyConfig,slice4KeyMode,4,{20,23})
DRV_DEF_SDK_F(PeRegBlk,1,AclPortKeyConfig,slice3KeyMode,4,{16,19})
DRV_DEF_SDK_F(PeRegBlk,1,AclPortKeyConfig,slice2KeyMode,4,{12,15})
DRV_DEF_SDK_F(PeRegBlk,1,AclPortKeyConfig,slice1KeyMode,4,{8,11})
DRV_DEF_SDK_F(PeRegBlk,1,AclPortKeyConfig,slice0KeyMode,4,{4,7})
DRV_DEF_SDK_F(PeRegBlk,1,AclPortKeyConfig,vidSel,2,{2,3})
DRV_DEF_SDK_F(PeRegBlk,1,AclPortKeyConfig,bitmapMode,1,{1,1})
DRV_DEF_SDK_F(PeRegBlk,1,AclPortKeyConfig,aclEn,1,{0,0})

DRV_DEF_SDK_D(PeRegBlk,1,AclRangeCheck,0x0008,OP_DIRECT,TBL_SRAM,12,2,0x00271600)
DRV_DEF_SDK_F(PeRegBlk,1,AclRangeCheck,valid,1,{34,34})
DRV_DEF_SDK_F(PeRegBlk,1,AclRangeCheck,optype,2,{32,33})
DRV_DEF_SDK_F(PeRegBlk,1,AclRangeCheck,maxVal,16,{16,31})
DRV_DEF_SDK_F(PeRegBlk,1,AclRangeCheck,minVal,16,{0,15})

DRV_DEF_D(PeRegBlk,1,AclQuadSliceConfig,0x0004,OP_DIRECT,TBL_SRAM,16,1,0x00271200)
DRV_DEF_F(PeRegBlk,1,AclQuadSliceConfig,quadMode,4,{0,3})

DRV_DEF_D(PeRegBlk,1,AclSliceKeyConfig,0x0004,OP_DIRECT,TBL_SRAM,8,1,0x00271300)
DRV_DEF_F(PeRegBlk,1,AclSliceKeyConfig,keyType,2,{0,1})

DRV_DEF_SDK_D(PeRegBlk,1,LoopbackProfile,0x0004,OP_DIRECT,TBL_SRAM,32,1,0x00291700)
DRV_DEF_SDK_F(PeRegBlk,1,LoopbackProfile,loopbackFwdMode,1,{30,30})
DRV_DEF_SDK_F(PeRegBlk,1,LoopbackProfile,l4portSwapEnable,1,{29,29})
DRV_DEF_SDK_F(PeRegBlk,1,LoopbackProfile,sipUnicastAct,2,{27,28})
DRV_DEF_SDK_F(PeRegBlk,1,LoopbackProfile,sipMulticastAct,1,{26,26})
DRV_DEF_SDK_F(PeRegBlk,1,LoopbackProfile,dipMulticastAct,1,{25,25})
DRV_DEF_SDK_F(PeRegBlk,1,LoopbackProfile,dipUnicastAct,1,{24,24})
DRV_DEF_SDK_F(PeRegBlk,1,LoopbackProfile,saUnicastAct,2,{22,23})
DRV_DEF_SDK_F(PeRegBlk,1,LoopbackProfile,saMulticastAct,1,{21,21})
DRV_DEF_SDK_F(PeRegBlk,1,LoopbackProfile,daMulticastAct,1,{20,20})
DRV_DEF_SDK_F(PeRegBlk,1,LoopbackProfile,daUnicastAct,1,{19,19})
DRV_DEF_SDK_F(PeRegBlk,1,LoopbackProfile,opcodeLsbZero,1,{18,18})
DRV_DEF_SDK_F(PeRegBlk,1,LoopbackProfile,icmpPingResp,1,{17,17})
DRV_DEF_SDK_F(PeRegBlk,1,LoopbackProfile,icmp2lsbSwap,1,{16,16})
DRV_DEF_SDK_F(PeRegBlk,1,LoopbackProfile,twampEdit,1,{15,15})
DRV_DEF_SDK_F(PeRegBlk,1,LoopbackProfile,ttlInsert,1,{14,14})
DRV_DEF_SDK_F(PeRegBlk,1,LoopbackProfile,slmResp,1,{13,13})
DRV_DEF_SDK_F(PeRegBlk,1,LoopbackProfile,rmepid,13,{0,12})

DRV_DEF_M(QosMemBlk,1) // 00100000
DRV_DEF_SDK_D(QosMemBlk,1,StcMeterCtrl,0x0008,OP_INDIRECT,TBL_SRAM,128,2,0x00100800)
DRV_DEF_SDK_F(QosMemBlk,1,StcMeterCtrl,dropThd,12,{25,36})
DRV_DEF_SDK_F(QosMemBlk,1,StcMeterCtrl,bucketGrain,3,{22,24})
DRV_DEF_SDK_F(QosMemBlk,1,StcMeterCtrl,refreshCnt,19,{3,21})
DRV_DEF_SDK_F(QosMemBlk,1,StcMeterCtrl,meterDelta,1,{2,2})
DRV_DEF_SDK_F(QosMemBlk,1,StcMeterCtrl,meterMode,1,{1,1})
DRV_DEF_SDK_F(QosMemBlk,1,StcMeterCtrl,meterEn,1,{0,0})

DRV_DEF_D(QosMemBlk,1,StcMeterCnt,0x0004,OP_INDIRECT,TBL_SRAM,128,1,0x00100c00)
DRV_DEF_F(QosMemBlk,1,StcMeterCnt,b0Cnt,29,{0,28})

DRV_DEF_SDK_D(QosMemBlk,1,PriLplcMapTable,0x0004,OP_INDIRECT,TBL_SRAM,1024,1,0x00102000)
DRV_DEF_SDK_F(QosMemBlk,1,PriLplcMapTable,localPri,4,{2,5})
DRV_DEF_SDK_F(QosMemBlk,1,PriLplcMapTable,localColor,2,{0,1})

DRV_DEF_SDK_D(QosMemBlk,1,LplcPriMapTable,0x0004,OP_INDIRECT,TBL_SRAM,1024,1,0x00103000)
DRV_DEF_SDK_F(QosMemBlk,1,LplcPriMapTable,dscp,6,{4,9})
DRV_DEF_SDK_F(QosMemBlk,1,LplcPriMapTable,scos,4,{0,3})

DRV_DEF_D(QosMemBlk,1,ColorMapTable,0x0010,OP_INDIRECT,TBL_SRAM,64,2,0x00105000)
DRV_DEF_F(QosMemBlk,1,ColorMapTable,mapLpEn,1,{44,44})
DRV_DEF_F(QosMemBlk,1,ColorMapTable,mapScosEn,1,{43,43})
DRV_DEF_F(QosMemBlk,1,ColorMapTable,mapDscpEn,1,{42,42})
DRV_DEF_F(QosMemBlk,1,ColorMapTable,redLp,4,{38,41})
DRV_DEF_F(QosMemBlk,1,ColorMapTable,yellowLp,4,{34,37})
DRV_DEF_F(QosMemBlk,1,ColorMapTable,greenLp,4,{30,33})
DRV_DEF_F(QosMemBlk,1,ColorMapTable,redScos,4,{26,29})
DRV_DEF_F(QosMemBlk,1,ColorMapTable,yellowScos,4,{22,25})
DRV_DEF_F(QosMemBlk,1,ColorMapTable,greenScos,4,{18,21})
DRV_DEF_F(QosMemBlk,1,ColorMapTable,redDscp,6,{12,17})
DRV_DEF_F(QosMemBlk,1,ColorMapTable,yellowDscp,6,{6,11})
DRV_DEF_F(QosMemBlk,1,ColorMapTable,greenDscp,6,{0,5})

DRV_DEF_SDK_D(QosMemBlk,1,IngressMeterCtrl,0x0010,OP_INDIRECT,TBL_SRAM,64,3,0x00110000)
DRV_DEF_SDK_F(QosMemBlk,1,IngressMeterCtrl,inserviceMode,1,{90,90})
DRV_DEF_SDK_F(QosMemBlk,1,IngressMeterCtrl,inserviceId,10,{80,89})
DRV_DEF_SDK_F(QosMemBlk,1,IngressMeterCtrl,dropMode,2,{78,79})
DRV_DEF_SDK_F(QosMemBlk,1,IngressMeterCtrl,colorMapIndex,6,{72,77})
DRV_DEF_SDK_F(QosMemBlk,1,IngressMeterCtrl,meterDelta,1,{71,71})
DRV_DEF_SDK_F(QosMemBlk,1,IngressMeterCtrl,meterLink,2,{69,70})
DRV_DEF_SDK_F(QosMemBlk,1,IngressMeterCtrl,cm,1,{68,68})
DRV_DEF_SDK_F(QosMemBlk,1,IngressMeterCtrl,meterMode,2,{66,67})
DRV_DEF_SDK_F(QosMemBlk,1,IngressMeterCtrl,bucketGrain,3,{63,65})
DRV_DEF_SDK_F(QosMemBlk,1,IngressMeterCtrl,b0Freshcount,19,{44,62})
DRV_DEF_SDK_F(QosMemBlk,1,IngressMeterCtrl,b0Bucketsize,12,{32,43})
DRV_DEF_SDK_F(QosMemBlk,1,IngressMeterCtrl,b1Freshcount,19,{13,31})
DRV_DEF_SDK_F(QosMemBlk,1,IngressMeterCtrl,b1Bucketsize,12,{1,12})
DRV_DEF_SDK_F(QosMemBlk,1,IngressMeterCtrl,meterEn,1,{0,0})

DRV_DEF_D(QosMemBlk,1,IngressMeterCnt,0x0008,OP_INDIRECT,TBL_SRAM,64,2,0x00118000)
DRV_DEF_F(QosMemBlk,1,IngressMeterCnt,b0Cnt,29,{29,57})
DRV_DEF_F(QosMemBlk,1,IngressMeterCnt,b1Cnt,29,{0,28})

DRV_DEF_SDK_D(QosMemBlk,1,IngressCounterCtrl,0x0004,OP_INDIRECT,TBL_SRAM,256,1,0x00134000)
DRV_DEF_SDK_F(QosMemBlk,1,IngressCounterCtrl,ctrl,3,{0,2})

DRV_DEF_SDK_D(QosMemBlk,1,IngressCounterTable,0x0010,OP_INDIRECT,TBL_SRAM,256,3,0x00120000)
DRV_DEF_SDK_F(QosMemBlk,1,IngressCounterTable,byteCnt,46,{32,77})
DRV_DEF_SDK_F(QosMemBlk,1,IngressCounterTable,frameCnt,32,{0,31})

DRV_DEF_D(QosMemBlk,1,IngressCounterTableView1,0x0010,OP_INDIRECT,TBL_SRAM,256,3,0x00120000)
DRV_DEF_F(QosMemBlk,1,IngressCounterTableView1,preDropByteCnt,39,{39,77})
DRV_DEF_F(QosMemBlk,1,IngressCounterTableView1,postDropByteCnt,39,{0,38})

DRV_DEF_SDK_D(QosMemBlk,1,IngressCounterTableView2,0x0010,OP_INDIRECT,TBL_SRAM,256,3,0x00120000)
DRV_DEF_SDK_F(QosMemBlk,1,IngressCounterTableView2,redFrameCnt,30,{48,77})
DRV_DEF_SDK_F(QosMemBlk,1,IngressCounterTableView2,yellowFrameCnt,16,{32,47})
DRV_DEF_SDK_F(QosMemBlk,1,IngressCounterTableView2,greenFrameCnt,32,{0,31})

DRV_DEF_D(QosMemBlk,1,IngressCounterTableView3,0x0010,OP_INDIRECT,TBL_SRAM,256,3,0x00120000)
DRV_DEF_F(QosMemBlk,1,IngressCounterTableView3,stcDropCnt,13,{65,77})
DRV_DEF_F(QosMemBlk,1,IngressCounterTableView3,meterDropCnt,13,{52,64})
DRV_DEF_F(QosMemBlk,1,IngressCounterTableView3,ircDropCnt,13,{39,51})
DRV_DEF_F(QosMemBlk,1,IngressCounterTableView3,vlanDropCnt,13,{26,38})
DRV_DEF_F(QosMemBlk,1,IngressCounterTableView3,arlDropCnt,13,{13,25})
DRV_DEF_F(QosMemBlk,1,IngressCounterTableView3,aclDropCnt,13,{0,12})

DRV_DEF_D(QosMemBlk,1,QosPortDropCnt,0x0020,OP_DIRECT,TBL_SRAM,15,6,0x00106400)
DRV_DEF_F(QosMemBlk,1,QosPortDropCnt,inCnt,32,{160,191})
DRV_DEF_F(QosMemBlk,1,QosPortDropCnt,outCnt,32,{128,159})
DRV_DEF_F(QosMemBlk,1,QosPortDropCnt,stcDropCnt,32,{96,127})
DRV_DEF_F(QosMemBlk,1,QosPortDropCnt,ircDropCnt,32,{64,95})
DRV_DEF_F(QosMemBlk,1,QosPortDropCnt,macroDrop,32,{32,63})
DRV_DEF_F(QosMemBlk,1,QosPortDropCnt,microDrop,32,{0,31})

DRV_DEF_M(QosRegBlk,1)
DRV_DEF_SDK_D(QosRegBlk,1,QosCpuAccessReq,0x0010,OP_DIRECT,TBL_SRAM,1,1,0x00106800)
DRV_DEF_SDK_F(QosRegBlk,1,QosCpuAccessReq,req,1,{31,31})
DRV_DEF_SDK_F(QosRegBlk,1,QosCpuAccessReq,reqType,1,{30,30})
DRV_DEF_SDK_F(QosRegBlk,1,QosCpuAccessReq,page,6,{24,29})
DRV_DEF_SDK_F(QosRegBlk,1,QosCpuAccessReq,addr,24,{0,23})

DRV_DEF_SDK_D(QosRegBlk,1,QosCpuAccessWdata,0x0020,OP_DIRECT,TBL_SRAM,1,8,0x00106840)
DRV_DEF_SDK_F(QosRegBlk,1,QosCpuAccessWdata,data,256,{0,255})

DRV_DEF_SDK_D(QosRegBlk,1,QosCpuAccessRdata,0x0040,OP_DIRECT,TBL_SRAM,1,9,0x00106880)
DRV_DEF_SDK_F(QosRegBlk,1,QosCpuAccessRdata,complete,1,{256,256})
DRV_DEF_SDK_F(QosRegBlk,1,QosCpuAccessRdata,data,256,{0,255})

DRV_DEF_SDK_D(QosRegBlk,1,GlbMeterCtrl,0x0010,OP_DIRECT,TBL_SRAM,1,2,0x00100000)
DRV_DEF_SDK_F(QosRegBlk,1,GlbMeterCtrl,bypassPtpIrcMeter,1,{34,34})
DRV_DEF_SDK_F(QosRegBlk,1,GlbMeterCtrl,bypassOamIrcMeter,1,{33,33})
DRV_DEF_SDK_F(QosRegBlk,1,GlbMeterCtrl,bypassAclIrcMeter,1,{32,32})
DRV_DEF_SDK_F(QosRegBlk,1,GlbMeterCtrl,bypassPtpStcMeter,1,{31,31})
DRV_DEF_SDK_F(QosRegBlk,1,GlbMeterCtrl,bypassOamStcMeter,1,{30,30})
DRV_DEF_SDK_F(QosRegBlk,1,GlbMeterCtrl,bypassAclStcMeter,1,{29,29})
DRV_DEF_SDK_F(QosRegBlk,1,GlbMeterCtrl,meterGapbyte,5,{24,28})
DRV_DEF_SDK_F(QosRegBlk,1,GlbMeterCtrl,meterBorrow,1,{23,23})
DRV_DEF_SDK_F(QosRegBlk,1,GlbMeterCtrl,ircStcLoc,2,{21,22})
DRV_DEF_SDK_F(QosRegBlk,1,GlbMeterCtrl,copyIrcEn,1,{20,20})
DRV_DEF_SDK_F(QosRegBlk,1,GlbMeterCtrl,dropIrcEn,1,{19,19})
DRV_DEF_SDK_F(QosRegBlk,1,GlbMeterCtrl,stcL2mcMode,1,{18,18})
DRV_DEF_SDK_F(QosRegBlk,1,GlbMeterCtrl,stcMlfMode,1,{17,17})
DRV_DEF_SDK_F(QosRegBlk,1,GlbMeterCtrl,copyStcEn,1,{16,16})
DRV_DEF_SDK_F(QosRegBlk,1,GlbMeterCtrl,dropStcEn,1,{15,15})
DRV_DEF_SDK_F(QosRegBlk,1,GlbMeterCtrl,dlfStcEn,1,{14,14})
DRV_DEF_SDK_F(QosRegBlk,1,GlbMeterCtrl,mlfStcEn,1,{13,13})
DRV_DEF_SDK_F(QosRegBlk,1,GlbMeterCtrl,l2mcStcEn,1,{12,12})
DRV_DEF_SDK_F(QosRegBlk,1,GlbMeterCtrl,bcStcEn,1,{11,11})
DRV_DEF_SDK_F(QosRegBlk,1,GlbMeterCtrl,dlfStcIndex,2,{9,10})
DRV_DEF_SDK_F(QosRegBlk,1,GlbMeterCtrl,mlfStcIndex,2,{7,8})
DRV_DEF_SDK_F(QosRegBlk,1,GlbMeterCtrl,l2mcStcIndex,2,{5,6})
DRV_DEF_SDK_F(QosRegBlk,1,GlbMeterCtrl,bcStcIndex,2,{3,4})
DRV_DEF_SDK_F(QosRegBlk,1,GlbMeterCtrl,ituMode,1,{2,2})
DRV_DEF_SDK_F(QosRegBlk,1,GlbMeterCtrl,ingressMeterMode,1,{1,1})
DRV_DEF_SDK_F(QosRegBlk,1,GlbMeterCtrl,egressMeterMode,1,{0,0})

DRV_DEF_D(QosRegBlk,1,EthRefreshCfg,0x0008,OP_DIRECT,TBL_SRAM,2,2,0x00100010)
DRV_DEF_F(QosRegBlk,1,EthRefreshCfg,multiParam,12,{24,35})
DRV_DEF_F(QosRegBlk,1,EthRefreshCfg,divParam,24,{0,23})

DRV_DEF_D(QosRegBlk,1,PortIrcAdmissionState,0x0004,OP_DIRECT,TBL_SRAM,29,1,0x00100080)
DRV_DEF_F(QosRegBlk,1,PortIrcAdmissionState,state,2,{0,1})

DRV_DEF_D(QosRegBlk,1,PortIrcMeterCtrl,0x0010,OP_DIRECT,TBL_SRAM,29,2,0x00100400)
DRV_DEF_F(QosRegBlk,1,PortIrcMeterCtrl,dropThd,12,{50,61})
DRV_DEF_F(QosRegBlk,1,PortIrcMeterCtrl,pauseThd,12,{38,49})
DRV_DEF_F(QosRegBlk,1,PortIrcMeterCtrl,cancelThd,12,{26,37})
DRV_DEF_F(QosRegBlk,1,PortIrcMeterCtrl,pauseEn,1,{25,25})
DRV_DEF_F(QosRegBlk,1,PortIrcMeterCtrl,bucketGrain,3,{22,24})
DRV_DEF_F(QosRegBlk,1,PortIrcMeterCtrl,refreshCnt,19,{3,21})
DRV_DEF_F(QosRegBlk,1,PortIrcMeterCtrl,meterDelta,1,{2,2})
DRV_DEF_F(QosRegBlk,1,PortIrcMeterCtrl,meterMode,1,{1,1})
DRV_DEF_F(QosRegBlk,1,PortIrcMeterCtrl,meterEn,1,{0,0})

DRV_DEF_SDK_D(QosRegBlk,1,PortStcMapping,0x0004,OP_DIRECT,TBL_SRAM,29,1,0x00100100)
DRV_DEF_SDK_F(QosRegBlk,1,PortStcMapping,dlfStcEn,1,{11,11})
DRV_DEF_SDK_F(QosRegBlk,1,PortStcMapping,mlfStcEn,1,{10,10})
DRV_DEF_SDK_F(QosRegBlk,1,PortStcMapping,l2mcStcEn,1,{9,9})
DRV_DEF_SDK_F(QosRegBlk,1,PortStcMapping,bcStcEn,1,{8,8})
DRV_DEF_SDK_F(QosRegBlk,1,PortStcMapping,dlfStcIndex,2,{6,7})
DRV_DEF_SDK_F(QosRegBlk,1,PortStcMapping,mlfStcIndex,2,{4,5})
DRV_DEF_SDK_F(QosRegBlk,1,PortStcMapping,l2mcStcIndex,2,{2,3})
DRV_DEF_SDK_F(QosRegBlk,1,PortStcMapping,bcStcIndex,2,{0,1})

DRV_DEF_SDK_D(QosRegBlk,1,PortStcBaseCtrl,0x0010,OP_DIRECT,TBL_SRAM,29,1,0x00100200)
DRV_DEF_SDK_F(QosRegBlk,1,PortStcBaseCtrl,portStcEn,1,{7,7})
DRV_DEF_SDK_F(QosRegBlk,1,PortStcBaseCtrl,stcBaseIndex,7,{0,6})

DRV_DEF_SDK_D(QosRegBlk,1,Lp2qpMapTable,0x0004,OP_DIRECT,TBL_SRAM,16,1,0x00104000)
DRV_DEF_SDK_F(QosRegBlk,1,Lp2qpMapTable,egportQp,3,{0,2})

DRV_DEF_SDK_D(QosRegBlk,1,CounterCtrl,0x0004,OP_DIRECT,TBL_SRAM,1,1,0x00136000)
DRV_DEF_SDK_F(QosRegBlk,1,CounterCtrl,cntRcEn,1,{0,0})

DRV_DEF_D(QosRegBlk,1,IntrusiveIngressMonState,0x0004,OP_DIRECT,TBL_SRAM,1,2,0x00106010)
DRV_DEF_F(QosRegBlk,1,IntrusiveIngressMonState,meterOverflow,1,{49,49})
DRV_DEF_F(QosRegBlk,1,IntrusiveIngressMonState,meterUnderflow,1,{48,48})
DRV_DEF_F(QosRegBlk,1,IntrusiveIngressMonState,secRate,32,{16,47})
DRV_DEF_F(QosRegBlk,1,IntrusiveIngressMonState,testNotGreenCnt,16,{0,15})

DRV_DEF_D(QosRegBlk,1,IntrusiveEgressMonState,0x0010,OP_DIRECT,TBL_SRAM,1,2,0x00106030)
DRV_DEF_F(QosRegBlk,1,IntrusiveEgressMonState,meterOverflow,1,{49,49})
DRV_DEF_F(QosRegBlk,1,IntrusiveEgressMonState,meterUnderflow,1,{48,48})
DRV_DEF_F(QosRegBlk,1,IntrusiveEgressMonState,secRate,32,{16,47})
DRV_DEF_F(QosRegBlk,1,IntrusiveEgressMonState,testNotGreenCnt,16,{0,15})

DRV_DEF_D(QosRegBlk,1,IngressIntrusiveAlmReg,0x0010,OP_DIRECT,TBL_SRAM,1,3,0x00106040)
DRV_DEF_F(QosRegBlk,1,IngressIntrusiveAlmReg,notGreenMeterId,11,{67,77})
DRV_DEF_F(QosRegBlk,1,IngressIntrusiveAlmReg,overflowMeterId,11,{56,66})
DRV_DEF_F(QosRegBlk,1,IngressIntrusiveAlmReg,underflowMeterId,11,{45,55})
DRV_DEF_F(QosRegBlk,1,IngressIntrusiveAlmReg,notGreenCnt,15,{30,44})
DRV_DEF_F(QosRegBlk,1,IngressIntrusiveAlmReg,overflowCnt,15,{15,29})
DRV_DEF_F(QosRegBlk,1,IngressIntrusiveAlmReg,underflowCnt,15,{0,14})

DRV_DEF_D(QosRegBlk,1,EgressIntrusiveAlmReg,0x0010,OP_DIRECT,TBL_SRAM,1,3,0x00106050)
DRV_DEF_F(QosRegBlk,1,EgressIntrusiveAlmReg,notGreenMeterId,8,{61,68})
DRV_DEF_F(QosRegBlk,1,EgressIntrusiveAlmReg,overflowMeterId,8,{53,60})
DRV_DEF_F(QosRegBlk,1,EgressIntrusiveAlmReg,underflowMeterId,8,{45,52})
DRV_DEF_F(QosRegBlk,1,EgressIntrusiveAlmReg,notGreenCnt,15,{30,44})
DRV_DEF_F(QosRegBlk,1,EgressIntrusiveAlmReg,overflowCnt,15,{15,29})
DRV_DEF_F(QosRegBlk,1,EgressIntrusiveAlmReg,underflowCnt,15,{0,14})

DRV_DEF_D(QosRegBlk,1,MeterMonCtrl,0x0010,OP_DIRECT,TBL_SRAM,1,1,0x00106060)
DRV_DEF_F(QosRegBlk,1,MeterMonCtrl,meterMonitorIndex,12,{1,12})
DRV_DEF_F(QosRegBlk,1,MeterMonCtrl,meterMonitorEn,1,{0,0})

DRV_DEF_D(QosRegBlk,1,MeterMonState,0x0010,OP_DIRECT,TBL_SRAM,1,2,0x00106070)
DRV_DEF_F(QosRegBlk,1,MeterMonState,bucket1Cnt,29,{29,57})
DRV_DEF_F(QosRegBlk,1,MeterMonState,bucket0Cnt,29,{0,28})

